Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.

Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Abstract: A chip package includes a substrate, a semiconductor chip, and a thermal conductive structure. The chip package includes a first and a second support structures below the thermal conductive structure. The first and the second support structures connect the substrate and corners of the thermal conductive structure. The thermal conductive structure has a side edge connecting the first and the second support structures. The first and the second support structures and the side edge together define of an opening exposing a space surrounding the semiconductor chip. The first and the second support structures are disposed along a side of the substrate. The first support structure is laterally separated from the side of the substrate by a first lateral distance. The side edge of the thermal conductive structure is laterally separated from the side of the substrate by a second lateral distance different than the first lateral distance.

Abstract: A semiconductor package is provided, which includes a first chip disposed over a first package substrate, a molding compound surrounding the first chip, a first thermal interface material disposed over the first chip and the molding compound, a heat spreader disposed over the thermal interface material, and a second thermal interface material disposed over the heat spreader. The first thermal interface material and the second thermal interface material have an identical width.

Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.

Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.

Abstract: A memory storage apparatus including a connector, a rewritable non-volatile memory module and a memory controller is provided. The memory controller receives a password to be verified, transforms the password into a data stream by using a first unit, generates a cipher text to be verified according to a predetermined data stream and the transformed data stream by using a second unit, and determines whether the cipher text to be verified is the same to a predetermined cipher text stored in the rewritable non-volatile memory module. When the cipher text to be verified is the same to the predetermined cipher text, the memory controller identifies that the password to be verified is validated. Accordingly, the memory storage apparatus can effectively verify a password input by a user, thereby protecting data stored in the rewritable non-volatile memory module.

Abstract: A data storage method for a flash memory storage device is provided. The method includes disposing a pattern identification unit in the flash memory storage device and disposing a pattern analysis unit in a host connected to the flash memory storage device. The method further includes analyzing a usage pattern of each flash memory storage address in the flash memory storage device by using the pattern analysis unit, receiving information from the pattern analysis unit through the pattern identification unit to identify the usage pattern of each flash memory storage address, and storing data into each flash memory storage address through a corresponding process according to the usage pattern of the flash memory storage address. Thereby, data can be stored according to the usage pattern of each flash memory storage address, and accordingly the speed of storing data into the flash memory storage device can be effectively increased.

Abstract: The present invention discloses a data access method accomplished by the following steps of: creating a predetermined password; generating a first encryption key; encrypting data based on the first encryption key; prompting for the predetermined password upon receipt of an access request; decoding a header of the NAND flash memory based on a user-entered password; examining the header to determine whether a mapping between the user-entered password and the first encryption key is defined; and decrypting and outputting the data by a decryption key when the mapping between the user-entered password and the first encryption key is defined.

Abstract: A data storage method for a flash memory storage device is provided. The method includes disposing a pattern identification unit in the flash memory storage device and disposing a pattern analysis unit in a host connected to the flash memory storage device. The method further includes analyzing a usage pattern of each flash memory storage address in the flash memory storage device by using the pattern analysis unit, receiving information from the pattern analysis unit through the pattern identification unit to identify the usage pattern of each flash memory storage address, and storing data into each flash memory storage address through a corresponding process according to the usage pattern of the flash memory storage address. Thereby, data can be stored according to the usage pattern of each flash memory storage address, and accordingly the speed of storing data into the flash memory storage device can be effectively increased.

Abstract: The present invention discloses a data access method accomplished by the following steps of: creating a predetermined password; generating a first encryption key; encrypting data based on the first encryption key; prompting for the predetermined password upon receipt of an access request; decoding a header of the NAND flash memory based on a user-entered password; examining the header to determine whether a mapping between the user-entered password and the first encryption key is defined; and decrypting and outputting the data by a decryption key when the mapping between the user-entered password and the first encryption key is defined.

Abstract: In an amplifier circuit with reduced power-off transients, an amplifier is provided for receiving an input signal and a reference signal to generate an output signal therefrom when it is enabled, and the amplifier is disabled when the supply voltage to the amplifier drops down to a threshold or to a level higher than the reference signal a threshold. The output stage transistor of the amplifier is applied with a body voltage to suppress the body diode parasitic to the output stage transistor to be forward-biased.

Abstract: In an amplifier circuit with reduced power-on transients, an amplifier has a gain to generate an output signal from an input signal and a reference signal when it is enabled, and a control circuit generates a control signal, based on the output signal and the reference signal, to be supplied to the amplifier during a power-on event. The amplifier is enabled by the control signal when the reference signal reaches the level of the output signal.

Abstract: In an amplifier circuit with reduced power-off transients, an amplifier is provided for receiving an input signal and a reference signal to generate an output signal therefrom when it is enabled, and the amplifier is disabled when the supply voltage to the amplifier drops down to a threshold or to a level higher than the reference signal a threshold. The output stage transistor of the amplifier is applied with a body voltage to suppress the body diode parasitic to the output stage transistor to be forward-biased.

Abstract: In an amplifier circuit with reduced power-on transients, an amplifier has a gain to generate an output signal from an input signal and a reference signal when it is enabled, and a control circuit generates a control signal, based on the output signal and the reference signal, to be supplied to the amplifier during a power-on event. The amplifier is enabled by the control signal when the reference signal reaches the level of the output signal.

Abstract: An in-situ purge system for charging the interior of a semiconductor wafer pod with nitrogen gas after the pod is exposed to ambient moisture, air and particles in a clean room. A gas supply line extends into the pod interior from a gas source, and a gas exhaust line extends from the pod interior to remove moisture, particles and excess gas from the pod interior as the pod contains a wafer-filled cassette and rests typically on a SMIF arm before transfer to a processing tool or other destination in the facility. The removable bottom door of the pod and the bottom plate of the cassette are modified to receive the gas supply line and the gas exhaust line.

Abstract: An in-situ purge system for charging the interior of a semiconductor wafer pod with nitrogen gas after the pod is exposed to ambient moisture, air and particles in a clean room. A gas supply line extends into the pod interior from a gas source, and a gas exhaust line extends from the pod interior to remove moisture, particles and excess gas from the pod interior as the pod contains a wafer-filled cassette and rests typically on a SMIF arm before transfer to a processing tool or other destination in the facility. The removable bottom door of the pod and the bottom plate of the cassette are modified to receive the gas supply line and the gas exhaust line.