Abstract: The present disclosure relates to a flash memory structure. The flash memory structure includes a first doped region and a second doped region disposed within a substrate. A select gate is disposed over the substrate between the first doped region and the second doped region. A floating gate is disposed over the substrate between the select gate and the first doped region, and a control gate is over the floating gate. The floating gate extends along multiple surfaces of the substrate.

Abstract: A vehicle rearview mirror includes a reflector having a light-transmissive pattern, and a light emitting module disposed behind the reflector and including a reflection base, a light source and a lens. The reflection base is hollow-shaped and provided on the inner wall thereof with a plurality of reflecting surfaces which gradually tilt one after another. The lens is mounted to the reflection base and has an inside surface and an outside surface. The inside surface is a matt surface. The outside surface faces the light-transmissive pattern. The light source is disposed on the reflection base in a way that the light emitted by the light source is reflected to the inside surface by the reflecting surfaces.

Abstract: A vehicle rearview mirror includes a reflector having a light-transmissive pattern, and a light emitting module including a case, a light source and a light guide. The light guide is disposed in the case and has an illuminating surface and a prism surface opposite to the illuminating surface for total reflection. The light guide is provided on a side thereof with an incidence surface. The light source is disposed in the case and faces the incidence surface in a way that the light emitted by the light source enters the light guide through the incidence surface and reflected by the prism surface to the illuminating surface which faces the light-transmissive pattern, thereby showing the light-transmissive pattern.

Abstract: A semiconductor device includes a substrate, a fin structure, an insulating layer, a select gate, a memory gate, and a charge trapping layer. The fin structure includes a first portion and a second extend from the substrate. Each of the first portion and the second portion includes a first sidewall and a second sidewall, and the second sidewalls are between the first sidewalls. The insulating layer is disposed between the second sidewalls of the first and second portions. The select gate and the memory gate extend across the fin structure and the insulating layer. The charge trapping layer is disposed between the memory gate and the select gate, between the memory gate and the insulating layer, and between the memory gate and the fin structure, and the second sidewalls of the first and second portions are free from in contact with the charge trapping layer.

Abstract: A light-emitting device including a substrate with a top surface and a bottom surface opposite to the top surface and a plurality of LED chips disposed on the top surface and configured to generate a top light visible above the top surface and a bottom light visible beneath the bottom surface, each LED chip comprising a plurality of light-emitting surfaces. The substrate has a thickness greater than 200 ?m and comprises aluminum oxide, sapphire, glass, plastic, or rubber. The plurality of LED chips has an incident light with a wavelength of 420-470 nm. The top light and the bottom light have a color temperature difference of not greater than 1500K.

Abstract: A computing device manages a router. A manager engine is instantiated based on a manager engine definition and instantiates a manager ESPE based on a created manager ESP model. A router configuration file is created based on mapping information read from the manager configuration file that describes connectivity between an event publishing source and a source window of the manager ESPE. A router engine is instantiated based on the created router configuration file. A connector is started to receive an event based on the router configuration file. The event is received in the source window of the manager ESPE processed based on the manager ESP model. A third computing device is selected by the router engine based on a usage metric received from each window of a plurality of windows defined by a remote ESP model configured to further process the processed event when it is received.

Abstract: A method and a device for increasing a laser induced shock wave pressure. According to the method, plasmas (21) are generated by impinging an aluminium foil (20) using lasers; a high-voltage pulse electrode (22) discharges to the plasmas (21) to induce and form a photoelectric combined energy field and then high-temperature plasmas (21) having the characteristics of an ultra-high density and an ultra-high speed expansion are induced and generated; a surface to be processed is impacted by the high-temperature plasmas (21) in a restrained state; the laser induced shock wave pressure is increased substantially; the surface of a high-strength material is reinforced, and the strength, hardness, abrasion resistance and anti-fatigue performances of the high-strength material are improved. The device comprises a laser, the electrode (22), a high-voltage power supply (4), a discharging medium (12), a moving platform, etc.

Abstract: A robot arm calibration device is provided, which includes a light emitter, a light sensing module, a cooperative motion controller and a processing module. The light emitter is disposed on at least one robot arm to emit a light beam. The light sensing module is disposed on at least another robot arm to receive the light beam and the light beam is converted into a plurality of image data. The cooperative motion controller is configured to drive the light emitter and light sensing module on at least two robot arms to a corrected position and a position to be corrected, respectively. The processing module receives the image data and the motion parameters of the at least two robot arms to calculate an error value between the corrected position and the position to be corrected, and analyzes the image data to output a corrected motion parameter for modifying motion command.

Abstract: The present invention provides an epitaxial structure of Ga-face group III nitride, its active device, and the method for fabricating the same. The epitaxial structure of Ga-face AlGaN/GaN comprises a substrate, an i-GaN (C-doped) layer on the substrate, an i-Al(y)GaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-Al(y)GaN buffer layer, and an i-Al(x)GaN layer on the i-GaN channel layer, where x=0.1˜0.3; y=0.05˜0.3, and x?y. By using the p-GaN inverted trapezoidal gate or anode structure in device design, the 2DEG in the epitaxial structure of Ga-face group III nitride below the p-GaN inverted trapezoidal structure will be depleted, and thus fabricating p-GaN gate enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs), p-GaN anode AlGaN/GaN Schottky barrier diodes (SBDs), or hybrid devices.

Abstract: In some embodiments, the present disclosure relates to a flash memory structure. The flash memory structure has a source region and a drain region disposed within a substrate. A select gate is disposed over the substrate between the source region and the drain region, and a floating gate is disposed over the substrate between the select gate and the source region. A control gate is disposed over the floating gate. The floating gate has sidewalls that define protrusions extending downward from a lower surface of the floating gate to define a recess within a bottom of the floating gate.

Abstract: Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.

Abstract: This disclosure is related to a non-contact tool center point calibration method for a robot arm, and the method comprises: obtaining a coordinate transformation relationship between a flange surface of the robot arm and cameras by a hand-eye calibration algorithm; constructing a space coordinate system by a stereoscopic reconstruction method; actuating a replaceable member fixed with the flange surface to present postures in a union field of view of the cameras sequentially, recording feature coordinates of the replaceable member in the space coordinate system, and recording flange surface coordinates which is under the postures in the space coordinate system; obtaining a transformation relationship between a tool center point and the flange surface; and updating the transformation relationship into a control program of the robot arm. Moreover, the disclosure further discloses a calibration device performing the calibration method and a robot arm system having the calibration function.

Abstract: The present invention provides an epitaxial structure of Ga-face group III nitride, its active device, and the method for fabricating the same. The epitaxial structure of Ga-face AlGaN/GaN comprises a substrate, a Buffer layer (C-doped) on the substrate, an i-GaN (C-doped) layer on the Buffer layer (C-doped), an i-Al(y)GaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-Al(y)GaN buffer layer, and an i-Al(x)GaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By using the p-GaN inverted trapezoidal gate or anode structure in device design, the 2DEG in the epitaxial structure of Ga-face group III nitride below the p-GaN inverted trapezoidal structure will be depleted, and thus fabricating p-GaN gate enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs), p-GaN anode AlGaN/GaN Schottky barrier diodes (SBDs), or hybrid devices.

Abstract: The present invention relates to a light emitting device comprising a transparent substrate which light can pass through and at least one LED chip emitting light omni-directionally. Wherein the LED chip is disposed on one surface of the substrate and the light emitting angle of the LED chip is wider than 180°, and the light emitted by the LED chip will penetrate into the substrate and at least partially emerge from another surface of the substrate. According to the present invention, the light emitting device using LED chips can provide sufficient lighting intensity and uniform lighting performance.

Abstract: An ion source head structure of a semiconductor ion implanter including a filament, a filament clamp, a cathode, a cathode clamp, an insulation assembly is provided. The filament clamp clamps the filament. The cathode presents a shell shape and has a receiving space. The filament is located in the receiving space. The cathode clamp clamps the cathode. The insulation assembly is disposed between the filament clamp and the cathode clamp such that the filament clamp is insulated from the cathode clamp. The insulation assembly has a first surface, a second surface opposite to the first surface, and an outer surface between the first surface and the second surface, wherein the first surface of the insulation assembly is in contact with the filament clamp, and the second surface of the insulation assembly is in contact with the cathode clamp. A step difference exists on the outer surface of the insulation assembly.

Abstract: A virtual assistant negotiation method is provided, which includes the following steps: transmitting an event information by a first electronic device corresponding to an initiator; receiving a plurality of candidate projects generated by second electronic devices corresponding to a plurality of participants according to the event information by the first electronic devices; selecting a portion of the candidate projects to serve as recommended projects by the first electronic device of the host; and making a decision according to the opinions, for the recommended projects, corresponding to the main participant among the participants by the first electronic device.

Abstract: An antenna module is provided, which includes a first antenna set and a second antenna set. The first antenna set includes a first transmitter end and a first receiver end, and provides a detection range, less than or substantially equal to 180°, in the direction of a first plane. The second antenna set includes a second transmitter end and a second receiver end, and provides a detection range, substantially equal to 180°, in the direction of a second plane. The polarization direction of the first antenna set is perpendicular to the polarization direction of the second antenna set; the first plane, the second plane and the plane where the antenna module is disposed are perpendicular to one another.

Abstract: The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-AlyGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-AlyGaN layer to the junction between the i-GaN channel layer and the i-AlxGaN layer.

Abstract: A semiconductor device includes a substrate, a conductive pad region electrically coupled to the substrate, a first dielectric layer over the conductive pad region, and a passivation layer over the first dielectric layer, wherein the passivation layer includes a laterally-extending portion covering the first dielectric layer and a vertically-extending portion on a sidewall of the first dielectric layer. The laterally-extending portion and the vertically-extending portion of the passivation layer are joined along a vertically-extending boundary.

Abstract: In some embodiments, the present disclosure relates to a flash memory structure. The flash memory structure has a source region and a drain region disposed within a substrate. A select gate is disposed over the substrate between the source region and the drain region, and a floating gate is disposed over the substrate between the select gate and the source region. A control gate is disposed over the floating gate. The floating gate has sidewalls that define protrusions extending downward from a lower surface of the floating gate to define a recess within a bottom of the floating gate.