Patents by Inventor Shu-Hui Chang
Shu-Hui Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11968869Abstract: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.Type: GrantFiled: April 28, 2022Date of Patent: April 23, 2024Assignee: InnoLux CorporationInventors: Ya-Wen Lin, Chien-Chih Chen, Yen-Hsi Tu, Cheng-Wei Chang, Shu-Hui Yang
-
Patent number: 11923352Abstract: A semiconductor device is provided. The semiconductor device comprises a first semiconductor die comprising a first capacitor, and a second semiconductor die in contact with the first semiconductor die and comprises a diode. The first semiconductor die and the second semiconductor die are arranged along a first direction, and a diode is configured to direct electrons accumulated at the first capacitor to a ground.Type: GrantFiled: January 28, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsin-Li Cheng, Shu-Hui Su, Yu-Chi Chang, Yingkit Felix Tsui, Shih-Fen Huang
-
Publication number: 20230251531Abstract: A display device includes a substrate, a transistor, a pixel electrode, a first conductive layer and a second conductive layer. The transistor is disposed on the substrate. The pixel electrode is disposed on the substrate. The pixel electrode is electrically connected to the transistor. The first conductive layer is disposed on the pixel electrode. The first conductive layer has a first slit. The second conductive layer is disposed on the pixel electrode. The second conductive layer has a second slit. The first slit and the second slit are overlapped with the pixel electrode.Type: ApplicationFiled: April 7, 2023Publication date: August 10, 2023Applicant: Innolux CorporationInventors: Feng-Ching Lin, Chia-Wei Tseng, Wen-Ming Hung, Shu-Hui Chang
-
Patent number: 11656508Abstract: A display device, including a substrate, a first transistor, a second transistor, a first pixel electrode, a second pixel electrode, and a common electrode layer, is provided. The first transistor and the second transistor are disposed on the substrate. The first pixel electrode is electrically connected to the first transistor. The second pixel electrode is electrically connected to the second transistor. The second pixel electrode is disposed adjacent to the first pixel electrode. The common electrode layer has a first slit. The first slit spans from the first pixel electrode to the second pixel electrode.Type: GrantFiled: January 12, 2022Date of Patent: May 23, 2023Assignee: Innolux CorporationInventors: Feng-Ching Lin, Chia-Wei Tseng, Wen-Ming Hung, Shu-Hui Chang
-
Publication number: 20220252948Abstract: A display device, including a substrate, a first transistor, a second transistor, a first pixel electrode, a second pixel electrode, and a common electrode layer, is provided. The first transistor and the second transistor are disposed on the substrate. The first pixel electrode is electrically connected to the first transistor. The second pixel electrode is electrically connected to the second transistor. The second pixel electrode is disposed adjacent to the first pixel electrode. The common electrode layer has a first slit. The first slit spans from the first pixel electrode to the second pixel electrode.Type: ApplicationFiled: January 12, 2022Publication date: August 11, 2022Applicant: Innolux CorporationInventors: Feng-Ching Lin, Chia-Wei Tseng, Wen-Ming Hung, Shu-Hui Chang
-
Patent number: 9312260Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: GrantFiled: April 13, 2011Date of Patent: April 12, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ali Keshavarzi, Ta-Pen Guo, Helen Shu-Hui Chang, Hsiang-Jen Tseng, Shyue-Shyh Lin, Lee-Chung Lu, Chung-Cheng Wu, Li-Chun Tien, Jung-Chan Yang, Shu-Min Chen, Min Cao, Yung-Chin Hou
-
Publication number: 20150349071Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a first contact having first contact dimensions that are relative to first gate dimensions of at least one of a first gate or a second gate, where relative refers to a specific relationship between the first contact dimensions and the first gate dimensions. The first contact is between the first gate and the second gate. The first contact having the first contact dimensions relative to the first gate dimensions has lower resistance with little to no increased capacitance, as compared to a semiconductor arrangement having first contact dimensions not in accordance with the specific relationship. The semiconductor arrangement having the lower resistance with little to no increased capacitance exhibits at least one of improved performance or reduced power requirements than a semiconductor arrangement that does not have such lower resistance with little to no increased capacitance.Type: ApplicationFiled: May 29, 2014Publication date: December 3, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chih-Liang Chen, Helen Shu-Hui Chang, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin
-
Patent number: 9184250Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a first contact having first contact dimensions that are relative to first gate dimensions of at least one of a first gate or a second gate, where relative refers to a specific relationship between the first contact dimensions and the first gate dimensions. The first contact is between the first gate and the second gate. The first contact having the first contact dimensions relative to the first gate dimensions has lower resistance with little to no increased capacitance, as compared to a semiconductor arrangement having first contact dimensions not in accordance with the specific relationship. The semiconductor arrangement having the lower resistance with little to no increased capacitance exhibits at least one of improved performance or reduced power requirements than a semiconductor arrangement that does not have such lower resistance with little to no increased capacitance.Type: GrantFiled: May 29, 2014Date of Patent: November 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chih-Liang Chen, Helen Shu-Hui Chang, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin
-
Patent number: 8698205Abstract: An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer.Type: GrantFiled: May 25, 2012Date of Patent: April 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiann-Tyng Tzeng, Chih-Liang Chen, Yi-Feng Chen, Kam-Tou Sio, Shang-Chih Hsieh, Helen Shu-Hui Chang
-
Patent number: 8643232Abstract: A stator manufacturing method for a motor includes an assembling step coupling a magnetic driving assembly onto an outer circumferential wall of a shaft tube, a mold combining step disposing the shaft tube and the magnetic driving assembly in an intra-cavity of a fixture unit, a glue injecting and forming step injecting a filling glue into the intra-cavity, with the filling glue solidifying into a protective glue coating with which the shaft tube and magnetic driving assembly are coated, a mold removing step removing the fixture unit from the shaft tube, magnetic driving assembly and protective glue coating, and a shaft tube seat coupling step providing a shaft tube seat having an engaging portion and coupling the engaging portion with the shaft tube, allowing the shaft tube, the magnetic driving assembly, the protective glue coating and the shaft tube seat to be coupled together to form a stator for the motor.Type: GrantFiled: January 31, 2011Date of Patent: February 4, 2014Assignee: Sunonwealth Electric Machine Industry Co., Ltd.Inventors: Ching-Sheng Hung, Kun-Li Hsieh, Shu-Hui Chang
-
Publication number: 20130313615Abstract: An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer.Type: ApplicationFiled: May 25, 2012Publication date: November 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jiann-Tyng TZENG, Chih-Liang CHEN, Yi-Feng CHEN, Kam-Tou SIO, Shang-Chih HSIEH, Helen Shu-Hui CHANG
-
Publication number: 20130077173Abstract: The present invention relates to a display screen mask structure using a shielding frame and a manufacturing method thereof. A combination of a shielding frame body and a plurality of substrate units, or a combination of a surface-printing outer frame portion and a surface-printing separated inner frame portion of a shielding frame body to be connectively overlapped on a single or multiple layers of light-transmitting thin film substrate, is overlapped on a self-light emitting display element of a photoelectric device panel. The light, scattered from the self-light emitting display element, is filtered and reflected by and concentratedly radiated from the outer frame portion and the separated inner frame portions of the shielding frame body, so that the light radiated from the self-light emitting display element of the photoelectric device panel is more concentratedly purified and has an enhanced color contrast of the dark tone.Type: ApplicationFiled: January 20, 2012Publication date: March 28, 2013Inventors: Rih-Yang WANG, Po-Tang Wang, Shu-Hui Chang
-
Publication number: 20130070342Abstract: The present invention is related to a display screen mask structure, providing a plurality of arranged and combined substrate units overlapped on a self-light emitting display element of a photoelectric device panel. The light, radiated from the self-light emitting display element, is filtered and reflected by and concentratedly radiated from a light-reflecting layer overlapped on the light-transmitting bodies of the substrate units, so that the light leakage can be prevented and an external strong light can be shielded by the light-shielding layer overlapped on the light-reflecting layer, the light generated from the self-light emitting display element can be efficiently concentrated, and the phenomenon such as whitening and low image contrast ratio occurred by an external light radiating on a display panel can be improved.Type: ApplicationFiled: January 19, 2012Publication date: March 21, 2013Inventors: Rih-Yang Wang, Po-Tang Wang, Yuan-Hsing Ko, Shu-Hui Chang
-
Publication number: 20120139387Abstract: A stator manufacturing method for a motor includes an assembling step coupling a magnetic driving assembly onto an outer circumferential wall of a shaft tube, a mold combining step disposing the shaft tube and the magnetic driving assembly in an intra-cavity of a fixture unit, a glue injecting and forming step injecting a filling glue into the intra-cavity, wherein the filling glue solidifies into a protective glue coating with which the shaft tube and magnetic driving assembly are coated, a mold removing step removing the fixture unit from the shaft tube, magnetic driving assembly and protective glue coating, and a shaft tube seat coupling step providing a shaft tube seat having an engaging portion and coupling the engaging portion with the shaft tube, allowing the shaft tube, the magnetic driving assembly, the protective glue coating and the shaft tube seat to be coupled together to form a stator for the motor.Type: ApplicationFiled: January 31, 2011Publication date: June 7, 2012Inventors: Ching-Sheng Hung, Kun-Li Hsieh, Shu-Hui Chang
-
Publication number: 20110291200Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: ApplicationFiled: April 13, 2011Publication date: December 1, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ali KESHAVARZI, Ta-Pen GUO, Helen Shu-Hui CHANG, Hsiang-Jen TSENG, Shyue-Shyh LIN, Lee-Chung LU, Chung-Cheng WU, Li-Chun TIEN, Jung-Chan YANG, Shu-Min CHEN, Min CAO, Yung-Chin HOU
-
Patent number: 7744716Abstract: A method for making a water-proof laminate from wood, includes a lower mold. A lower cover is provided in the lower mold. A wood plate is provided on the lower cover in the lower mold. An upper cover is provided on the wood plate. An upper mold is provided for pressing the lower cover, the wood plate and lower cover against the lower mold. A coating is injected into the upper and lower molds to cover at least the edges of the upper mold, wood plate and lower mold so that a water-proof laminate is finished after the curing of the coating. The upper mold is moved from the lower mold, and the water-proof laminate is moved from the lower mold.Type: GrantFiled: February 14, 2007Date of Patent: June 29, 2010Inventor: Shu-Hui Chang
-
Publication number: 20090085850Abstract: A liquid crystal display device that operates in optically compensated bend mode includes a gate driving circuit, a data driving circuit, and pixel units. The gate driving circuit is configured for providing a gate signal to each of the pixel units. The data driving circuit is configured for providing a first voltage corresponding to a black signal in a first sub frame of a frame divided into two sub frames to each of the pixel units via a corresponding data line, and a second voltage corresponding to a gray level display signal in a second sub frame of the frame to each of the pixel units.Type: ApplicationFiled: September 29, 2008Publication date: April 2, 2009Inventors: I-An Yao, Shu-Hui Chang, Hung-Lin Ko, Chueh-Ju Chen, Chiu-Lien Yang
-
Publication number: 20080191385Abstract: A method is provided for making a water-proof laminate from wood. In the method, a lower mold is provided. A lower cover is provided in the lower mold. A wood plate is provided on the lower cover in the lower mold. An upper cover is provided on the wood plate. An upper mold is provided for pressing the lower cover, the wood plate and lower cover against the lower mold. A coating is injected into the upper and lower molds to cover at least the edges of the upper mold, wood plate and lower mold so that a water-proof laminate is finished after the curing of the coating. The upper mold is moved from the lower mold and the water-proof laminate is moved from the lower mold.Type: ApplicationFiled: February 14, 2007Publication date: August 14, 2008Inventor: Shu-Hui Chang
-
Patent number: D754774Type: GrantFiled: November 20, 2013Date of Patent: April 26, 2016Assignee: DiCon Fiberoptics, Inc.Inventors: Shu-Hui Chang, Sung-Ching Wu, Jui-Hung Cheng, Brent John Siebenaler
-
Patent number: D781470Type: GrantFiled: December 22, 2015Date of Patent: March 14, 2017Assignee: DiCon Fiberoptics, Inc.Inventors: Yen-Ta Hsieh, Shu-Hui Chang, Cheng-Ting Yen, Jui-Hung Cheng