Patents by Inventor Shu-Hui Sung
Shu-Hui Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230197723Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: ApplicationFiled: February 13, 2023Publication date: June 22, 2023Inventors: Ali KESHAVARZI, Ta-Pen GUO, Shu-Hui SUNG, Hsiang-Jen TSENG, Shyue-Shyh LIN, Lee-Chung LU, Chung-Cheng WU, Li-Chun TIEN, Jung-Chan YANG, Ting Yu CHEN, Min CAO, Yung-Chin HOU
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Patent number: 11581314Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: GrantFiled: December 20, 2019Date of Patent: February 14, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ali Keshavarzi, Ta-Pen Guo, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin, Lee-Chung Lu, Chung-Cheng Wu, Li-Chun Tien, Jung-Chan Yang, Ting Yu Chen, Min Cao, Yung-Chin Hou
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Publication number: 20200126986Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: ApplicationFiled: December 20, 2019Publication date: April 23, 2020Inventors: Ali KESHAVARZI, Ta-Pen GUO, Shu-Hui SUNG, Hsiang-Jen TSENG, Shyue-Shyh LIN, Lee-Chung LU, Chung-Cheng WU, Li-Chun TIEN, Jung-Chan YANG, Ting-Yu CHEN, Min CAO, Yung-Chin HOU
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Patent number: 10535655Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: GrantFiled: April 8, 2016Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ali Keshavarzi, Ta-Pen Guo, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin, Lee-Chung Lu, Chung-Cheng Wu, Li-Chun Tien, Jung-Chan Yang, Ting-Yu Chen, Min Cao, Yung-Chin Hou
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Patent number: 9917050Abstract: A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.Type: GrantFiled: October 21, 2016Date of Patent: March 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Chih-Liang Chen, Chih-Ming Lai, Kam-Tou Sio, Ru-Gun Liu, Meng-Hung Shen, Chun-Hung Liou, Shu-Hui Sung, Charles Chew-Yuen Young
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Patent number: 9754881Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation: 0.2 ? ? P gate ? ? min + 0.35 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min - 20 0.2 ? ? L gate ? ? min + 0.8 ? ? H gate ? ? min - 5 × 0.3 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min + 5 38 ? 0.32 Pgate min is the minimum value among gate pitches of the gate structures, and Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.Type: GrantFiled: February 22, 2016Date of Patent: September 5, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Liang Chen, Chih-Ming Lai, Yung-Sung Yen, Kam-Tou Sio, Tsong-Hua Ou, Chun-Kuang Chen, Ru-Gun Liu, Shu-Hui Sung, Charles Chew-Yuen Young
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Patent number: 9659115Abstract: Among other things, one or more systems and techniques for analyzing a tiered semiconductor structure are provided. One or more segments are defined for the tiered semiconductor structure. The one or more segments are iteratively evaluated during electrical simulation while taking into account thermal properties to determine power metrics for the segments. The power metrics are used to determine temperatures generated by integrated circuitry within the segments. Responsive to a segment having a temperature above a temperature threshold, a temperature action plan, such as providing an alert or inserting one or more thermal release structures into the segment, is implemented. In this way, the one or more segments are iteratively evaluated to identify and resolve thermal and reliability issues.Type: GrantFiled: December 19, 2013Date of Patent: May 23, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chih-Liang Chen, Jiann-Tyng Tzeng, Shu-Hui Sung, Charles Chew-Yuen Young
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Publication number: 20170040259Abstract: A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.Type: ApplicationFiled: October 21, 2016Publication date: February 9, 2017Inventors: Chih-Liang Chen, Chih-Ming Lai, Kam-Tou Sio, Ru-Gun Liu, Meng-Hung Shen, Chun-Hung Liou, Shu-Hui Sung, Charles Chew-Yuen Young
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Publication number: 20160372469Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: ApplicationFiled: April 8, 2016Publication date: December 22, 2016Inventors: Ali Keshavarzi, Ta-Pen Guo, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin, Lee-Chung Lu, Chung-Cheng Wu, Li-Chun Tien, Jung-Chan Yang, Ting-Yu Chen, Min Cao, Yung-Chin Hou
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Method of forming semiconductor device including source/drain contact having height below gate stack
Patent number: 9478636Abstract: Provided is a semiconductor device and methods of forming the same. The semiconductor device includes a substrate having source/drain regions and a channel region between the source/drain regions; a gate structure over the substrate and adjacent to the channel region; source/drain contacts over the source/drain regions and electrically connecting to the source/drain regions; and a contact protection layer over the source/drain contacts. The gate structure includes a gate stack and a spacer. A top surface of the source/drain contacts is lower than a top surface of the spacer, which is substantially co-planar with a top surface of the contact protection layer. The contact protection layer prevents accidental shorts between the gate stack and the source/drain regions when gate vias are formed over the gate stack. Therefore, gate vias may be formed over any portion of the gate stack, even in areas that overlap the channel region from a top view.Type: GrantFiled: May 16, 2014Date of Patent: October 25, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Liang Chen, Chih-Ming Lai, Kam-Tou Sio, Ru-Gun Liu, Meng-Hung Shen, Chun-Hung Liou, Shu-Hui Sung, Charles Chew-Yuen Young -
Publication number: 20160172297Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation: 0.2 ? ? P gate ? ? min + 0.35 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min - 20 0.2 ? ? L gate ? ? min + 0.8 ? ? H gate ? ? min - 5 × 0.3 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min + 5 38 ? 0.32 Pgate min is the minimum value among gate pitches of the gate structures, and Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.Type: ApplicationFiled: February 22, 2016Publication date: June 16, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Liang CHEN, Chih-Ming LAI, Yung-Sung YEN, Kam-Tou SIO, Tsong-Hua OU, Chun-Kuang CHEN, Ru-Gun LIU, Shu-Hui SUNG, Charles Chew-Yuen YOUNG
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Patent number: 9281273Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate and a contact formed adjacent to the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. In addition, some of the metal layers include metal lines extending in the first direction, and some of the metal layers include metal lines extending in a second direction substantially perpendicular to the first direction. Furthermore, the gate structures follow the following equation: 0.2 ? ? P gate ? ? min + 0.35 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min - 20 0.2 ? ? L gate ? ? min + 0.8 ? ? H gate ? ? min - 5 × 0.3 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min + 5 38 ? 0.32 Pgate min is the minimum value among gate pitches of the gate structures.Type: GrantFiled: September 3, 2014Date of Patent: March 8, 2016Assignee: Taiwan Semiconductor Manufacturing Co., LTD.Inventors: Chih-Liang Chen, Chih-Ming Lai, Yung-Sung Yen, Kam-Tou Sio, Tsong-Hua Ou, Chun-Kuang Chen, Ru-Gun Liu, Shu-Hui Sung, Charles Chew-Yuen Young
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Publication number: 20160064322Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate and a contact formed adjacent to the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. In addition, some of the metal layers include metal lines extending in the first direction, and some of the metal layers include metal lines extending in a second direction substantially perpendicular to the first direction. Furthermore, the gate structures follow the following equation: 0.2 ? ? P gate ? ? min + 0.35 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min - 20 0.2 ? ? L gate ? ? min + 0.8 ? ? H gate ? ? min - 5 × 0.3 ? ? L gate ? ? min + 0.3 ? ? H gate ? ? min + 5 38 ? 0.32 Pgate min is the minimum value among gate pitches of the gate structures.Type: ApplicationFiled: September 3, 2014Publication date: March 3, 2016Inventors: Chih-Liang CHEN, Chih-Ming LAI, Yung-Sung YEN, Kam-Tou SIO, Tsong-Hua OU, Chun-Kuang CHEN, Ru-Gun LIU, Shu-Hui SUNG, Charles Chew-Yuen YOUNG
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Publication number: 20150332962Abstract: Provided is a semiconductor device and methods of forming the same. The semiconductor device includes a substrate having source/drain regions and a channel region between the source/drain regions; a gate structure over the substrate and adjacent to the channel region; source/drain contacts over the source/drain regions and electrically connecting to the source/drain regions; and a contact protection layer over the source/drain contacts. The gate structure includes a gate stack and a spacer. A top surface of the source/drain contacts is lower than a top surface of the spacer, which is substantially co-planar with a top surface of the contact protection layer. The contact protection layer prevents accidental shorts between the gate stack and the source/drain regions when gate vias are formed over the gate stack. Therefore, gate vias may be formed over any portion of the gate stack, even in areas that overlap the channel region from a top view.Type: ApplicationFiled: May 16, 2014Publication date: November 19, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Liang Chen, Chih-Ming Lai, Kam-Tou Sio, Ru-Gun Liu, Meng-Hung Shen, Chun-Hung Liou, Shu-Hui Sung, Charles Chew-Yuen Young
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Publication number: 20150179529Abstract: Among other things, one or more systems and techniques for analyzing a tiered semiconductor structure are provided. One or more segments are defined for the tiered semiconductor structure. The one or more segments are iteratively evaluated during electrical simulation while taking into account thermal properties to determine power metrics for the segments. The power metrics are used to determine temperatures generated by integrated circuitry within the segments. Responsive to a segment having a temperature above a temperature threshold, a temperature action plan, such as providing an alert or inserting one or more thermal release structures into the segment, is implemented. In this way, the one or more segments are iteratively evaluated to identify and resolve thermal and reliability issues.Type: ApplicationFiled: December 19, 2013Publication date: June 25, 2015Inventors: Chih-Liang Chen, Jiann-Tyng Tzeng, Shu-Hui Sung, Charles Chew-Yuen Young