Patents by Inventor Shu-Jen Fang

Shu-Jen Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9386326
    Abstract: Techniques for synchronizing error concealment during video decoding include determining a decoding error. A recovery point within a current frame is determined for each decoding error. The determined recovery point may be the start of the next good slice of a frame after the current frame containing the error. The number of macroblock to be concealed is also determined. The determined number of macroblocks from the recovery point may then be concealed in hardware or software. The techniques for concealing errors may also include determining available macroblocks for use in concealing the error. The techniques for concealing errors may further include selecting a given concealment mode.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: July 5, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Krishna Kishor Noru, Nitin Jadon, Shu-Jen Fang, Prahlad Venkatapuram, Visalakshi Vaduganathan
  • Patent number: 9069706
    Abstract: Efficient and effective permission confidential information protection systems and methods are described. The secure information protection systems and methods facilitate storage of confidential information in a manner safe from rogue software access. In one embodiment, a confidential information protection method is implemented in hardware and facilitates protection against software and/or Operating System hacks. In one exemplary implementation, a confidential information protection method includes setting a permission sticky bit flag to a default state upon system set up. The permission sticky bit flag access permission indication is adjusted at system reset in accordance with an initial application instruction. Access to the confidential information is restricted in accordance with the permission sticky bit and the permission sticky bit is protected from adjustments attempting to violate the permission indication.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: June 30, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Parthasarathy Sriram, Gordon Grigor, Shu-Jen Fang
  • Publication number: 20140098898
    Abstract: Techniques for synchronizing error concealment during video decoding include determining a decoding error. A recovery point within a current frame is determined for each decoding error. The determined recovery point may be the start of the next good slice of a frame after the current frame containing the error. The number of macroblock to be concealed is also determined. The determined number of macroblocks from the recovery point may then be concealed in hardware or software. The techniques for concealing errors may also include determining available macroblocks for use in concealing the error. The techniques for concealing errors may further include selecting a given concealment mode.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Krishna Kishor Noru, Nitin Jadon, Shu-Jen Fang, Prahlad Venkatapuram, Visalakshi Vaduganathan
  • Patent number: 8448002
    Abstract: A clock module is coupled in parallel to a number of data processing modules that are coupled in series. The data processing modules can be individually clock-gated. Each of the data processing modules can determine whether or not it can be placed into an idle state. To reduce power consumption, any subset of the data processing modules that are eligible to be placed in an idle state can be clock-gated. The remaining data processing modules can continue to receive clock signals from the clock module and thus can continue to process data.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: May 21, 2013
    Assignee: Nvidia Corporation
    Inventors: Ravi Bulusu, Shu-Jen Fang, Srivatsan Varadarajan, Han Chou, Sandro Pintz, Aiyun Wang
  • Publication number: 20090259862
    Abstract: A clock module is coupled in parallel to a number of data processing modules that are coupled in series. The data processing modules can be individually clock-gated. Each of the data processing modules can determine whether or not it can be placed into an idle state. To reduce power consumption, any subset of the data processing modules that are eligible to be placed in an idle state can be clock-gated. The remaining data processing modules can continue to receive clock signals from the clock module and thus can continue to process data.
    Type: Application
    Filed: April 10, 2008
    Publication date: October 15, 2009
    Applicant: NVIDIA CORPORATION
    Inventors: Ravi Bulusu, Shu-Jen Fang, Srivatsan Varadarajan, Han Chou, Sandro Pintz, Aiyun Wang
  • Publication number: 20090205053
    Abstract: Efficient and effective permission confidential information protection systems and methods are described. The secure information protection systems and methods facilitate storage of confidential information in a manner safe from rogue software access. In one embodiment, a confidential information protection method is implemented in hardware and facilitates protection against software and/or Operating System hacks. In one exemplary implementation, a confidential information protection method includes setting a permission sticky bit flag to a default state upon system set up. The permission sticky bit flag access permission indication is adjusted at system reset in accordance with an initial application instruction. Access to the confidential information is restricted in accordance with the permission sticky bit and the permission sticky bit is protected from adjustments attempting to violate the permission indication.
    Type: Application
    Filed: February 11, 2008
    Publication date: August 13, 2009
    Inventors: Parthasarathy Sriram, Gordon Grigor, Shu-Jen Fang