Patents by Inventor Shu-Jen Sung

Shu-Jen Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090146311
    Abstract: An interconnect structure is disposed on a substrate with a conductive part thereon and includes a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a first UV cutting layer at least between the first porous low-k layer and the second porous low-k layer. The damascene structure is electrically connected with the conductive part. The UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.
    Type: Application
    Filed: February 13, 2009
    Publication date: June 11, 2009
    Applicant: United Microelectronics Corp.
    Inventors: Feng-Yu Hsu, Chih-Chien Liu, Chun-Chieh Huang, Jei-Ming Chen, Shu-Jen Sung
  • Patent number: 7514347
    Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV cutting layer at least between the first and the second porous low-k layers, wherein the UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: April 7, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Feng-Yu Hsu, Chih-Chien Liu, Chun-Chieh Huang, Jei-Ming Chen, Shu-Jen Sung
  • Patent number: 7348272
    Abstract: A method of fabricating interconnect is described. A first dielectric layer having an opening is formed over a substrate. A metal layer is filled into the opening. A material layer is formed over the first dielectric layer and the metal layer. A surface treatment process is performed to the material layer so as to form a cap layer on the surface of the metal layer. The material layer and a portion of the first dielectric layer are removed. A second dielectric layer is formed over the substrate, and the surface of the second dielectric layer is higher than that of the cap layer. A planarization process is performed at least to remove a portion of the second dielectric layer and a portion of the cap layer so as to expose the top of the opening.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: March 25, 2008
    Assignee: United Microelectronics Corp.
    Inventor: Shu-Jen Sung
  • Publication number: 20070085210
    Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV cutting layer at least between the first and the second porous low-k layers, wherein the UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.
    Type: Application
    Filed: January 26, 2006
    Publication date: April 19, 2007
    Inventors: Feng-Yu Hsu, Chih-Chien Liu, Chun-Chieh Huang, Jei-Ming Chen, Shu-Jen Sung
  • Publication number: 20070032058
    Abstract: A method of fabricating interconnect is described. A first dielectric layer having an opening is formed over a substrate. A metal layer is filled into the opening. A material layer is formed over the first dielectric layer and the metal layer. A surface treatment process is performed to the material layer so as to form a cap layer on the surface of the metal layer. The material layer and a portion of the first dielectric layer are removed. A second dielectric layer is formed over the substrate, and the surface of the second dielectric layer is higher than that of the cap layer. A planarization process is performed at least to remove a portion of the second dielectric layer and a portion of the cap layer so as to expose the top of the opening.
    Type: Application
    Filed: August 3, 2005
    Publication date: February 8, 2007
    Inventor: Shu-Jen Sung