Abstract: A package substrate for improving electrical performance includes at least an insulating layer, a wiring layer and a ground/power layer. The wiring layer is formed on a top surface of the insulating layer, and includes a plurality of inner fingers, a plurality of outer fingers and a metal ring. A plurality of inner through holes are formed through the insulating layer to electrically connect corresponding inner fingers to bottom surface of the insulating layer. The ground/power layer has a plurality of openings formed on a bottom surface of the insulating layer. The plurality of inner through holes are crowded in groups to pass through the openings which are electrically isolated from the ground/power layer. Each group of the inner through holes are arranged in grid array or radial arrangement so that a distance between two adjacent openings not less than 0.2 mm for improving electrical performance of the ground/power layer.

Abstract: A package substrate for improving electrical performance includes at least an insulating layer, a wiring layer and a ground/power layer. The wiring layer is formed on a top surface of the insulating layer, and includes a plurality of inner fingers, a plurality of outer fingers and a metal ring. A plurality of inner through holes are formed through the insulating layer to electrically connect corresponding inner fingers to bottom surface of the insulating layer. The ground/power layer has a plurality of openings formed on a bottom surface of the insulating layer. The plurality of inner through holes are crowded in groups to pass through the openings which are electrically isolated from the ground/power layer. Each group of the inner through holes are arranged in grid array or radial arrangement so that a distance between two adjacent openings not less than 0.2 mm for improving electrical performance of the ground/power layer.

Abstract: A BGA semiconductor package comprises a chip mounted on the central region of the upper surface on the substrate. The substrate includes an upper surface, a lower surface, a ground plate disposed under the upper surface, and at least one power plate disposed between the ground plate and the lower surface. A ground ring surrounds the periphery of the chip and possesses a first set of serrated portions extending toward the outer edge of the substrate. A first power ring surrounds the ground ring and possesses a second set of serrated portions extending among the first set of serrated portions of the ground ring, such that the extending portions of the first and second sets of serrated rings interlace coincidentally with each other and the wire bonding distances from the bonding pads of chip surface to the extending portions of the first and the second serrated rings are comparable.

Abstract: A substrate for use in packaging of a semiconductor chip is disclosed. The upper surface of the substrate comprises a die covering area adapted for receiving the chip, a ground ring and a power ring. The lower surface of the substrate comprises a plurality of first contact pads right under the vicinity of the ground ring and the power ring, and a plurality of second contact pads surrounding the first contact pads. It is noted that the first contact pads are divided into a two groups electrically connected to the ground ring and the power ring, respectively. Preferably, the lower surface of the substrate is further provided with a plurality of dummy pads at a position right under the periphery of the die covering area and a plurality of third contact pads located right under the die covering area.

Abstract: A substrate for use in packaging of a semiconductor chip having opposing upper and lower surfaces has a lower surface which comprises an outer array of contact pads, a center array of contact pads and a plurality of intermediate pads located between the outer array of contact pads and the center array of contact pads. All of the intermediate pads are electrically connected to the ground ring.