Patents by Inventor Shu-Jung Tseng
Shu-Jung Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369193Abstract: A semiconductor package includes: a substrate; a first dielectric layer over the substrate; a first bond pad and a second bond pad over the first dielectric layer, the first bond pad having a first sidewall facing the second bond pad; a second dielectric layer over the first and the second bond pads; and an opening through the second dielectric layer and extending from the first bond pad to the second bond pad, the opening including a first area over and exposing the first bond pad, where in a top view, the opening exposes a first segment of the first sidewall disposed between a first edge and a second edge of the first area that intersect the first sidewall, where the first segment of the first sidewall is between a second segment and a third segment of the first sidewall, the second segment being covered by the second dielectric layer.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Shu-Jung Tseng, Shyue-Ter Leu
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Patent number: 11817382Abstract: A semiconductor package includes: a substrate; a first dielectric layer over the substrate; a first bond pad and a second bond pad over the first dielectric layer, the first bond pad having a first sidewall facing the second bond pad; a second dielectric layer over the first and the second bond pads; and an opening through the second dielectric layer and extending from the first bond pad to the second bond pad, the opening including a first area over and exposing the first bond pad, where in a top view, the opening exposes a first segment of the first sidewall disposed between a first edge and a second edge of the first area that intersect the first sidewall, where the first segment of the first sidewall is between a second segment and a third segment of the first sidewall, the second segment being covered by the second dielectric layer.Type: GrantFiled: February 14, 2022Date of Patent: November 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Jung Tseng, Shyue-Ter Leu
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Publication number: 20230170291Abstract: A semiconductor package includes an interposer, a die and a first encapsulant. The die is bonded to the interposer, the die has a protective layer thereon, wherein the protective layer and the interposer are disposed on opposite sides of the die, and the protective layer is not extended beyond an outer sidewall of the die. The first encapsulant is disposed aside the die and the protective layer.Type: ApplicationFiled: February 1, 2023Publication date: June 1, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Jung Tseng, Fu-Jen Li
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Patent number: 11600562Abstract: A semiconductor package includes an interposer, a die, a protective layer, a plurality of first electrical connectors and a first molding material. The die includes a first surface and a second surface opposite to the first surface, and the die is bonded to the interposer through the first surface. The protective layer is disposed on the second surface of the die. The first electrical connectors are disposed aside the die. The first molding material is disposed aside the die, the protection layer and the first electrical connectors.Type: GrantFiled: October 21, 2020Date of Patent: March 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Jung Tseng, Fu-Jen Li
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Publication number: 20230060520Abstract: Disclosed are semiconductor packages and semiconductor devices. In one embodiment, a semiconductor package includes a package, a first integrated passive device, and a second integrated passive device. The first integrated passive device is disposed below the package. The second integrated passive device is disposed between the package and the first integrated passive device. The first integrated passive device is electrically connected to the package through the second integrated passive device.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Jung Tseng, Hui-Chang Yu
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Publication number: 20220165655Abstract: A semiconductor package includes: a substrate; a first dielectric layer over the substrate; a first bond pad and a second bond pad over the first dielectric layer, the first bond pad having a first sidewall facing the second bond pad; a second dielectric layer over the first and the second bond pads; and an opening through the second dielectric layer and extending from the first bond pad to the second bond pad, the opening including a first area over and exposing the first bond pad, where in a top view, the opening exposes a first segment of the first sidewall disposed between a first edge and a second edge of the first area that intersect the first sidewall, where the first segment of the first sidewall is between a second segment and a third segment of the first sidewall, the second segment being covered by the second dielectric layer.Type: ApplicationFiled: February 14, 2022Publication date: May 26, 2022Inventors: Shu-Jung Tseng, Shyue-Ter Leu
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Publication number: 20220122909Abstract: A semiconductor package includes an interposer, a die, a protective layer, a plurality of first electrical connectors and a first molding material. The die includes a first surface and a second surface opposite to the first surface, and the die is bonded to the interposer through the first surface. The protective layer is disposed on the second surface of the die. The first electrical connectors are disposed aside the die. The first molding material is disposed aside the die, the protection layer and the first electrical connectors.Type: ApplicationFiled: October 21, 2020Publication date: April 21, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Jung Tseng, Fu-Jen Li
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Patent number: 11251114Abstract: A semiconductor package includes: a substrate; a first dielectric layer over the substrate; a first bond pad and a second bond pad over the first dielectric layer, the first bond pad having a first sidewall facing the second bond pad; a second dielectric layer over the first and the second bond pads; and an opening through the second dielectric layer and extending from the first bond pad to the second bond pad, the opening including a first area over and exposing the first bond pad, where in a top view, the opening exposes a first segment of the first sidewall disposed between a first edge and a second edge of the first area that intersect the first sidewall, where the first segment of the first sidewall is between a second segment and a third segment of the first sidewall, the second segment being covered by the second dielectric layer.Type: GrantFiled: August 6, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Jung Tseng, Shyue-Ter Leu
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Publication number: 20210343633Abstract: A semiconductor package includes: a substrate; a first dielectric layer over the substrate; a first bond pad and a second bond pad over the first dielectric layer, the first bond pad having a first sidewall facing the second bond pad; a second dielectric layer over the first and the second bond pads; and an opening through the second dielectric layer and extending from the first bond pad to the second bond pad, the opening including a first area over and exposing the first bond pad, where in a top view, the opening exposes a first segment of the first sidewall disposed between a first edge and a second edge of the first area that intersect the first sidewall, where the first segment of the first sidewall is between a second segment and a third segment of the first sidewall, the second segment being covered by the second dielectric layer.Type: ApplicationFiled: August 6, 2020Publication date: November 4, 2021Inventors: Shu-Jung Tseng, Shyue-Ter Leu
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Patent number: 7521266Abstract: A method for reducing the scrap rate of fuse structures after laser repairing is provided. The method includes providing a semiconductor wafer comprising integrated circuits, performing a yield test on the semiconductor wafer to determine defective circuits, predetermining a wavelength limit, and keeping the semiconductor wafer away from lights having wavelengths lower than the wavelength limit. The defects on the semiconductors wafer are repaired by burning laser fuses. For copper-based fuse structures, the wavelength limit is about 550 nm.Type: GrantFiled: April 28, 2006Date of Patent: April 21, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Jung Tseng, Chi Chang Su, Chien-Wu Chu, You-Wen Yau, Long Sheng Yeou
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Publication number: 20070111402Abstract: A method for reducing the scrap rate of fuse structures after laser repairing is provided. The method includes providing a semiconductor wafer comprising integrated circuits, performing a yield test on the semiconductor wafer to determine defective circuits, predetermining a wavelength limit, and keeping the semiconductor wafer away from lights having wavelengths lower than the wavelength limit. The defects on the semiconductors wafer are repaired by burning laser fuses. For copper-based fuse structures, the wavelength limit is about 550 nm.Type: ApplicationFiled: April 28, 2006Publication date: May 17, 2007Inventors: Shu-Jung Tseng, Chi Su, Chien-Wu Chu, You-Wen Yau, Long Yeou
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Patent number: 6957116Abstract: A quality assurance system and method for use between a service provider having a sequence of process stages and a quality assurance stage, and a control center. The service provider performs a plurality of processes on goods at the process stages, transfers engineering data corresponding to the processes to the control center via Internet, and holds the goods at the quality assurance. The control center compares the engineering data with a standard specification, and transfers a confirmation message to the service provider if the engineering data conforms to the standard specification. The service provider may ship the goods to customers after the confirmation message is received.Type: GrantFiled: October 3, 2003Date of Patent: October 18, 2005Assignee: Taiwan Semiconductor Manufcturing Co., Ltd.Inventors: Jung-Yi Tsai, Chao-Yu Chang, Chui-Chung Chiu, Shu-Jung Tseng
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Publication number: 20050075749Abstract: A quality assurance system and method for use between a service provider having a sequence of process stages and a quality assurance stage, and a control center. The service provider performs a plurality of processes on goods at the process stages, transfers engineering data corresponding to the processes to the control center via Internet, and holds the goods at the quality assurance. The control center compares the engineering data with a standard specification, and transfers a confirmation message to the service provider if the engineering data conforms to the standard specification. The service provider may ship the goods to customers after the confirmation message is received.Type: ApplicationFiled: October 3, 2003Publication date: April 7, 2005Inventors: Jung-Yi Tsai, Chao-Yu Chang, Chui-Chung Chiu, Shu-Jung Tseng