Abstract: A memory is provided. The memory includes a control chip (114) and a plurality of memory chips (100). The plurality of memory chips are electrically connected to the control chip (114) by sharing a channel (01). The plurality of memory chips (100) are configured to adopt the same clock signal, and each of the plurality of memory chips (100) is configured to perform information interaction with the control chip (114) in a different clock state of the clock signal.

Abstract: A memory is provided. The memory includes a control chip (114) and a plurality of memory chips (100). The plurality of memory chips are electrically connected to the control chip (114) by sharing a channel (01). The plurality of memory chips (100) are configured to adopt the same clock signal, and each of the plurality of memory chips (100) is configured to perform information interaction with the control chip (114) in a different clock state of the clock signal.

Abstract: A chip stack package is provided. The chip stack package includes an n number of chips stacked on each other and an n number of interconnection strands connecting the chips. The interconnection strands are spirally rotated and insulated from each other. In one embodiment, the chips are substantially structurally identical. In another embodiment, each of the interconnection strands is electrically coupled to a chip selection signal.

Abstract: A measured device coupled to test equipment providing at least two test factors and receiving a test result is disclosed. The measured device includes a combinatorial logic circuit and a main circuit. The combinatorial logic circuit includes a first storage module and a second storage module. The first storage module stores the test factors according to a first operation clock. The second storage module stores and outputs at least two output factors according to a second operation clock. The frequency of the second operation clock is higher than the frequency of the first operation clock. When the test factors are stored in the first storage module, the test factors stored in the first storage module are served as the output factors and the output factors are output and stored in the second storage module. The main circuit generates the test result according to the output factors output by the second storage module.

Abstract: A chip stack package is provided. The chip stack package includes an n number of chips stacked on each other and an n number of interconnection strands connecting the chips. The interconnection strands are spirally rotated and insulated from each other. In one embodiment, the chips are substantially structurally identical. In another embodiment, each of the interconnection strands is electrically coupled to a chip selection signal.

Abstract: A measured device coupled to test equipment providing at least two test factors and receiving a test result is disclosed. The measured device includes a combinatorial logic circuit and a main circuit. The combinatorial logic circuit includes a first storage module and a second storage module. The first storage module stores the test factors according to a first operation clock. The second storage module stores and outputs at least two output factors according to a second operation clock. The frequency of the second operation clock is higher than the frequency of the first operation clock. When the test factors are stored in the first storage module, the test factors stored in the first storage module are served as the output factors and the output factors are output and stored in the second storage module. The main circuit generates the test result according to the output factors output by the second storage module.

Abstract: A memory access control method is provided. By decoding a read-write command, a mode register set (MRS) signal is generated. When the MRS signal is enabled, a latch outputs a bank-select signal. The bank-select signal is then decoded to generate a register-select signal. Then, an address signal is written into a register selected by the register-select signal. The value of a certain register can be used to determine whether to enable the error check function. Thus, the next generation memory structure with the CRC function can be compatible with the conventional memory structure.

Abstract: A random access memory data resetting method is provided. The method includes following steps. First, a state machine resetting signal is provided to a RAM. Next, the state machine resetting signal is extended for a predetermined time period. Afterwards, a data resetting operation is executed in the RAM within the predetermined time period.

Abstract: A memory access control method is provided. By decoding a read-write command, a mode register set (MRS) signal is generated. When the MRS signal is enabled, a latch outputs a bank-select signal. The bank-select signal is then decoded to generate a register-select signal. Then, an address signal is written into a register selected by the register-select signal. The value of a certain register can be used to determine whether to enable the error check function. Thus, the next generation memory structure with the CRC function can be compatible with the conventional memory structure.

Abstract: A semiconductor chip package is provided. The semiconductor chip package comprises a package substrate having a first surface and a second surface opposite to the first surface. A through hole extends through the package substrate. A semiconductor chip is disposed on the first surface of the package substrate, wherein a bottom surface of the semiconductor chip covers one end of the through hole. At least two bonding fingers are disposed on the second surface of the package substrate and arranged on sides of the through hole. A conductive line is disposed on the second surface of the package substrate and between the two bonding fingers and the through hole, wherein two terminals of the conductive line are electrically connected to the two bonding fingers, respectively.

Abstract: A random access memory data resetting method is provided. The method includes following steps. First, a state machine resetting signal is provided to a RAM. Next, the state machine resetting signal is extended for a predetermined time period. Afterwards, a data resetting operation is executed in the RAM within the predetermined time period.

Abstract: A random access memory and a data refreshing method thereof are provided. The random access memory includes a memory array having a plurality of word lines; a control logic unit which is used for outputting a refreshment indicating signal, a thermal sensor which is used for outputting a temperature indicating signal; a refresh counter which is used for outputting a row address counting signal; and a row address decoder which is used for performing a decoding operation on the row address counting signal in response to the refreshment indicating signal and the temperature indicating signal, and simultaneously enabling the plurality of word lines of the memory array based on a result of the decoding operation.

Abstract: A connector socket includes a housing with a slot for receiving a connecting portion of memory module; a side plate disposed inside the slot and mounted on an inner sidewall of the slot; at least two rows of sleeves alternately arranged and mounted on the side plate; a plurality of first conductive arms having first conductive distal terminals, passing through corresponding upper row of the at least two rows of sleeves; a plurality of second conductive arms having second conductive distal terminals, passing through corresponding lower row of the at least two rows of sleeves; and a pushing member on the housing for pushing the resilient side plate such that the first conductive distal terminals can contact with an upper row of fingers on the connecting portion, while the second conductive distal terminals can contact with a lower row of fingers on the connecting portion.

Abstract: A mark-shaped pad. A bonding pad structure with at least one mark-shaped bonding pad comprises: a bottom metal layer disposed over the surface of a rectangular semiconductor substrate to connect the circuit electrically, an inter-metal dielectric layer disposed over the bottom metal layer, metal plugs formed in the inter-metal dielectric layer to connect with the bottom metal layer, a top metal layer disposed over the inter-metal dielectric layer connecting with the metal plugs, and a passivation layer disposed over the top metal layer with openings to expose the top metal layer portions as bonding pads, wherein at least one bonding pad is mark-shaped, e.g. , , or , to indicate the orientation of the bonding pads on the rectangular semiconductor substrate.

Abstract: A mark-shaped pad. A bonding pad structure with at least one mark-shaped bonding pad comprises: a bottom metal layer disposed over the surface of a rectangular semiconductor substrate to connect the circuit electrically, an inter-metal dielectric layer disposed over the bottom metal layer, metal plugs formed in the inter-metal dielectric layer to connect with the bottom metal layer, a top metal layer disposed over the inter-metal dielectric layer connecting with the metal plugs, and a passivation layer disposed over the top metal layer with openings to expose the top metal layer portions as bonding pads, wherein at least one bonding pad is mark-shaped, e.g. “”, “”, “” or “”, to indicate the orientation of the bonding pads on the rectangular semiconductor substrate.

Abstract: A method of aligning a wafer and masks. In the present invention, a wafer having a surface with a plurality of fields and scribe lines is provided, and an initial mask and a subsequent mask are provided. The initial mask and the subsequent mask have a first pattern and a second pattern respectively corresponding to the fields, and have a plurality of original alignment marks at the corners thereof. The first pattern is transferred to the fields and a plurality of secondary alignment marks corresponding to the original alignment marks are formed at the corners of the fields by the initial mask. An intra-field alignment is performed to transfer the second pattern to each field by aligning the original alignment marks with the secondary alignment marks at the corner of each field.

Abstract: A mark-shaped pad. A bonding pad structure with at least one mark-shaped bonding pad comprises: a bottom metal layer disposed over the surface of a rectangular semiconductor substrate to connect the circuit electrically, an inter-metal dielectric layer disposed over the bottom metal layer, metal plugs formed in the inter-metal dielectric layer to connect with the bottom metal layer, a top metal layer disposed over the inter-metal dielectric layer connecting with the metal plugs, and a passivation layer disposed over the top metal layer with openings to expose the top metal layer portions as bonding pads, wherein at least one bonding pad is mark-shaped, e.g. “”, “”, “” or “”, to indicate the orientation of the bonding pads on the rectangular semiconductor substrate.

Abstract: A semiconductor memory device. One desired word line of a memory unit is turned on according to the row select signal, and a first delay circuit delays the column select signal a first determined time and outputs to a sense amplifier circuit. The sense amplifier circuit senses the desired word line, amplifies and outputs desired data to a latch circuit according to the column select signal. After that, the memory device can start to access the next data. Further, the delayed column select signal is also output to a second delay circuit to delay a second predetermined time as an output enable signal, and the latch circuit outputs the latched data according to the output enable signal.

Abstract: A mark-shaped pad. A bonding pad structure with at least one mark-shaped bonding pad comprises: a bottom metal layer disposed over the surface of a rectangular semiconductor substrate to connect the circuit electrically, an inter-metal dielectric layer disposed over the bottom metal layer, metal plugs formed in the inter-metal dielectric layer to connect with the bottom metal layer, a top metal layer disposed over the inter-metal dielectric layer connecting with the metal plugs, and a passivation layer disposed over the top metal layer with openings to expose the top metal layer portions as bonding pads, wherein at least one bonding pad is mark-shaped, e.g. “”, “”, “” or “”, to indicate the orientation of the bonding pads on the rectangular semiconductor substrate.

Abstract: A compression test circuit. The circuit tests a memory array, wherein the memory array has a plurality of memory cells pre-programmed with a test bit, each outputting an output bit. The compression test circuit comprises a compression unit, a transfer circuit and an output comparison unit. The compression test circuit outputs an output signal of logic one or logic zero according to the test bit written into the predetermined number of the memory cells, and outputs an error signal when at least one defective memory cell is detected.