Abstract: Disclosed is a wafer-level stacked chip assembly, comprising a plurality of chip layers vertically stacked together with vertically electrical interconnections between the adjacent chip layers realized by TSVs (Through Silicon Via). Each chip layer includes a switching mechanism for selectively bypassing chip coding sequence to deactivate failed IC area and its chip coding sequence, thereby the interconnection relationship among the chip layers can be re-defined and the function and chip code of the failed IC area can be deactivated. Accordingly, any known failed chip in the wafer-level stacking chip assembly can be controlled as a dummy chip to realize the wafer-level chip stacking of non-known good dices with exclusion of failed chip(s).

Abstract: Measuring device of the present invention includes a plurality of measuring sites for generating a plurality of optical paths and various dilutions. The range for concentration measurement and the measurement accuracy are enhanced due to the plurality of optical path length, and the interference on the measurement ranges and results caused by the concentration or the turbidity of suspended solid is reduced and removed by water sample dilution, and thus the characteristic wavelengths of the components in the water are measured. Next, the information of spectrum database is used to determine the ingredients which may exist in the water (qualitative analysis), and UV-VIS-NIR absorbance spectrum analysis is used to obtain the concentration of the respective ingredients in the water at the same time (quantitative analysis).

Abstract: Measuring device of the present invention includes a plurality of measuring sites for generating a plurality of optical paths and various dilutions. The range for concentration measurement and the measurement accuracy are enhanced due to the plurality of optical path length, and the interference on the measurement ranges and results caused by the concentration or the turbidity of suspended solid is reduced and removed by water sample dilution, and thus the characteristic wavelengths of the components in the water are measured. Next, the information of spectrum database is used to determine the ingredients which may exist in the water (qualitative analysis), and UV-VIS-NIR absorbance spectrum analysis is used to obtain the concentration of the respective ingredients in the water at the same time (quantitative analysis).

Abstract: Disclosed is a wafer-level stacked chip assembly, comprising a plurality of chip layers vertically stacked together with vertically electrical interconnections between the adjacent chip layers realized by TSVs (Through Silicon Via). Each chip layer includes a switching mechanism for selectively bypassing chip coding sequence to deactivate failed IC area and its chip coding sequence, thereby the interconnection relationship among the chip layers can be re-defined and the function and chip code of the failed IC area can be deactivated. Accordingly, any known failed chip in the wafer-level stacking chip assembly can be controlled as a dummy chip to realize the wafer-level chip stacking of non-known good dices with exclusion of failed chip(s).

Abstract: Measuring device of the present invention includes a plurality of measuring sites for generating a plurality of optical paths and various dilutions. The range for concentration measurement and the measurement accuracy are enhanced due to the plurality of optical path length, and the interference on the measurement ranges and results caused by the concentration or the turbidity of suspended solid is reduced and removed by water sample dilution, and thus the characteristic wavelengths of the components in the water are measured. Next, the information of spectrum database is used to determine the ingredients which may exist in the water (qualitative analysis), and UV-VIS-NIR absorbance spectrum analysis is used to obtain the concentration of the respective ingredients in the water at the same time (quantitative analysis).

Abstract: A proxy server including a system manager and a database is provided. The system manager includes an internal registrar module, an external registrar module, a session manager module and a signal routing module. The internal registrar module provides an internal register service for a plurality of nodes in a first service network. The external registrar module registers at an internet service provider providing network services in a second service network. The session manager module manages session processes in the first service network and the second service network and manages the network services shared between the registered nodes. The signal routing module routes control signals of the session processes between the first service network and the second service network. The database stores information related to the registered nodes.

Abstract: A chip stack package is provided. The chip stack package includes an n number of chips stacked on each other and an n number of interconnection strands connecting the chips. The interconnection strands are spirally rotated and insulated from each other. In one embodiment, the chips are substantially structurally identical. In another embodiment, each of the interconnection strands is electrically coupled to a chip selection signal.

Abstract: A measured device coupled to test equipment providing at least two test factors and receiving a test result is disclosed. The measured device includes a combinatorial logic circuit and a main circuit. The combinatorial logic circuit includes a first storage module and a second storage module. The first storage module stores the test factors according to a first operation clock. The second storage module stores and outputs at least two output factors according to a second operation clock. The frequency of the second operation clock is higher than the frequency of the first operation clock. When the test factors are stored in the first storage module, the test factors stored in the first storage module are served as the output factors and the output factors are output and stored in the second storage module. The main circuit generates the test result according to the output factors output by the second storage module.

Abstract: A drug detection apparatus for identifying whether a gas sample contains an acidic gas includes a reactor having a gas inlet, a detection reagent containing an oxidant and a reductant, and a catalyst triggering a chemical adsorption with the oxidant and the reductant. A drug detection method applied to a drug detection apparatus is also disclosed. The drug detection apparatus and method can detect the acidic gases from drugs immediately, sensitively and selectively, thereby improving the efficiency of suspect inspection of drug smuggling in airports.

Abstract: A chip stack package is provided. The chip stack package includes an n number of chips stacked on each other and an n number of interconnection strands connecting the chips. The interconnection strands are spirally rotated and insulated from each other. In one embodiment, the chips are substantially structurally identical. In another embodiment, each of the interconnection strands is electrically coupled to a chip selection signal.

Abstract: A measured device coupled to test equipment providing at least two test factors and receiving a test result is disclosed. The measured device includes a combinatorial logic circuit and a main circuit. The combinatorial logic circuit includes a first storage module and a second storage module. The first storage module stores the test factors according to a first operation clock. The second storage module stores and outputs at least two output factors according to a second operation clock. The frequency of the second operation clock is higher than the frequency of the first operation clock. When the test factors are stored in the first storage module, the test factors stored in the first storage module are served as the output factors and the output factors are output and stored in the second storage module. The main circuit generates the test result according to the output factors output by the second storage module.

Abstract: A proxy server including a system manager and a database is provided. The system manager includes an internal registrar module, an external registrar module, a session manager module and a signal routing module. The internal registrar module provides an internal register service for a plurality of nodes in a first service network. The external registrar module registers at an internet service provider providing network services in a second service network. The session manager module manages session processes in the first service network and the second service network and manages the network services shared between the registered nodes. The signal routing module routes control signals of the session processes between the first service network and the second service network. The database stores information related to the registered nodes.

Abstract: A memory access control method is provided. By decoding a read-write command, a mode register set (MRS) signal is generated. When the MRS signal is enabled, a latch outputs a bank-select signal. The bank-select signal is then decoded to generate a register-select signal. Then, an address signal is written into a register selected by the register-select signal. The value of a certain register can be used to determine whether to enable the error check function. Thus, the next generation memory structure with the CRC function can be compatible with the conventional memory structure.

Abstract: A random access memory data resetting method is provided. The method includes following steps. First, a state machine resetting signal is provided to a RAM. Next, the state machine resetting signal is extended for a predetermined time period. Afterwards, a data resetting operation is executed in the RAM within the predetermined time period.

Abstract: A memory access control method is provided. By decoding a read-write command, a mode register set (MRS) signal is generated. When the MRS signal is enabled, a latch outputs a bank-select signal. The bank-select signal is then decoded to generate a register-select signal. Then, an address signal is written into a register selected by the register-select signal. The value of a certain register can be used to determine whether to enable the error check function. Thus, the next generation memory structure with the CRC function can be compatible with the conventional memory structure.

Abstract: A semiconductor chip package is provided. The semiconductor chip package comprises a package substrate having a first surface and a second surface opposite to the first surface. A through hole extends through the package substrate. A semiconductor chip is disposed on the first surface of the package substrate, wherein a bottom surface of the semiconductor chip covers one end of the through hole. At least two bonding fingers are disposed on the second surface of the package substrate and arranged on sides of the through hole. A conductive line is disposed on the second surface of the package substrate and between the two bonding fingers and the through hole, wherein two terminals of the conductive line are electrically connected to the two bonding fingers, respectively.

Abstract: A random access memory data resetting method is provided. The method includes following steps. First, a state machine resetting signal is provided to a RAM. Next, the state machine resetting signal is extended for a predetermined time period. Afterwards, a data resetting operation is executed in the RAM within the predetermined time period.

Abstract: A random access memory and a data refreshing method thereof are provided. The random access memory includes a memory array having a plurality of word lines; a control logic unit which is used for outputting a refreshment indicating signal, a thermal sensor which is used for outputting a temperature indicating signal; a refresh counter which is used for outputting a row address counting signal; and a row address decoder which is used for performing a decoding operation on the row address counting signal in response to the refreshment indicating signal and the temperature indicating signal, and simultaneously enabling the plurality of word lines of the memory array based on a result of the decoding operation.

Abstract: A connector socket includes a housing with a slot for receiving a connecting portion of memory module; a side plate disposed inside the slot and mounted on an inner sidewall of the slot; at least two rows of sleeves alternately arranged and mounted on the side plate; a plurality of first conductive arms having first conductive distal terminals, passing through corresponding upper row of the at least two rows of sleeves; a plurality of second conductive arms having second conductive distal terminals, passing through corresponding lower row of the at least two rows of sleeves; and a pushing member on the housing for pushing the resilient side plate such that the first conductive distal terminals can contact with an upper row of fingers on the connecting portion, while the second conductive distal terminals can contact with a lower row of fingers on the connecting portion.

Abstract: A grease protecting apparatus (10) includes a heat sink (12) defining a plurality of receiving cavities (124) therein, a layer of grease (16) spread on a surface (122) of the heat sink, and a grease cover (14) attached to the surface of the heat sink for protecting the grease from contamination. The cover includes a main body (142) defining a protecting space (143) therein for covering the grease, two wings (144) extending from two opposite sides of the main body, and a plurality of projections (148) extending from the wings for being snapped in the receiving cavities of the heat sink. The projection has a trapezium-shaped cross section.