Patents by Inventor Shu-Ling Garver

Shu-Ling Garver has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100268931
    Abstract: In one embodiment, the present invention includes a method for performing dynamic testing of a many-core processor including a plurality of cores, manipulating data obtained from the dynamic testing into profile information of the many-core processor, and storing the profile information in a non-volatile memory. The non-volatile memory may be within the many-core processor, in some embodiments. Other embodiments are described and claimed.
    Type: Application
    Filed: June 28, 2010
    Publication date: October 21, 2010
    Inventors: Shekhar Borkar, Yatin Hoskote, Shu-Ling Garver
  • Patent number: 7774590
    Abstract: In one embodiment, the present invention includes a method for performing dynamic testing of a many-core processor including a plurality of cores, manipulating data obtained from the dynamic testing into profile information of the many-core processor, and storing the profile information in a non-volatile memory. The non-volatile memory may be within the many-core processor, in some embodiments. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: August 10, 2010
    Assignee: Intel Corporation
    Inventors: Shekhar Borkar, Yatin Hoskote, Shu-Ling Garver
  • Patent number: 7568115
    Abstract: According to embodiments of the disclosed subject matter in this application, a power management system with multiple voltage regulator (“VRs”) may be used to supply power to cores in a many-core processor. Each VR may supply power to a core or a part of a core. Different VRs may provide multiple voltages to a core/part in the many-core processor. The value of the output voltage of a VR may be modulated under the direction of the core/part to which the voltage regulator supplies power. In one embodiment, the multiple VRs may be integrated with cores in a single die. In another embodiment, the power management system with multiple VRs may be on a die (“the VR die”) separate from the die of the many-core processor. The VR die may be included in the same package as the many-core processor die.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: July 28, 2009
    Assignee: Intel Corporation
    Inventors: Shekhar Borkar, Tanay Karnik, Shu-ling Garver
  • Patent number: 7412353
    Abstract: According to embodiments of the disclosed subject matter, cores in a many-core processor may be periodically tested to obtain and/or refresh their dynamic profiles. The dynamic profile of a core may include information on its maximum operating frequency, power consumption, power leakage, functional correctness, and other parameters, as well as the trending information of these parameters. Once a dynamic profile has been created for each core, cores in a many-core processor may be grouped into different bins according to their characteristics. Based on dynamic profiles and the grouping information, the operating system (“OS”) or other software may allocate a task to those cores that are most suitable for the task. The interconnect fabric in the many-core processor may be reconfigured to ensure a high level of connectivity among the selected cores. Additionally, cores may be re-allocated and/or re-balanced to a task in response to changes in the environment.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: August 12, 2008
    Assignee: Intel Corporation
    Inventors: Shekhar Borkar, Yatin Hoskote, Shu-Ling Garver
  • Publication number: 20070226482
    Abstract: In one embodiment, the present invention includes a method for performing dynamic testing of a many-core processor including a plurality of cores, manipulating data obtained from the dynamic testing into profile information of the many-core processor, and storing the profile information in a non-volatile memory. The non-volatile memory may be within the many-core processor, in some embodiments. Other embodiments are described and claimed.
    Type: Application
    Filed: March 23, 2006
    Publication date: September 27, 2007
    Inventors: Shekhar Borkar, Yatin Hoskote, Shu-Ling Garver
  • Publication number: 20070074011
    Abstract: According to embodiments of the disclosed subject matter, cores in a many-core processor may be periodically tested to obtain and/or refresh their dynamic profiles. The dynamic profile of a core may include information on its maximum operating frequency, power consumption, power leakage, functional correctness, and other parameters, as well as the trending information of these parameters. Once a dynamic profile has been created for each core, cores in a many-core processor may be grouped into different bins according to their characteristics. Based on dynamic profiles and the grouping information, the operating system (“OS”) or other software may allocate a task to those cores that are most suitable for the task. The interconnect fabric in the many-core processor may be reconfigured to ensure a high level of connectivity among the selected cores. Additionally, cores may be re-allocated and/or re-balanced to a task in response to changes in the environment.
    Type: Application
    Filed: September 28, 2005
    Publication date: March 29, 2007
    Inventors: Shekhar Borkar, Yatin Hoskote, Shu-Ling Garver
  • Publication number: 20070070673
    Abstract: According to embodiments of the disclosed subject matter in this application, a power management system with multiple voltage regulator (“VRs”) may be used to supply power to cores in a many-core processor. Each VR may supply power to a core or a part of a core. Different VRs may provide multiple voltages to a core/part in the many-core processor. The value of the output voltage of a VR may be modulated under the direction of the core/part to which the voltage regulator supplies power. In one embodiment, the multiple VRs may be integrated with cores in a single die. In another embodiment, the power management system with multiple VRs may be on a die (“the VR die”) separate from the die of the many-core processor. The VR die may be included in the same package as the many-core processor die.
    Type: Application
    Filed: September 28, 2005
    Publication date: March 29, 2007
    Inventors: Shekhar Borkar, Tanay Karnik, Shu-ling Garver