Patents by Inventor Shu-Ming Yip

Shu-Ming Yip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006276
    Abstract: The present disclosure relates to manufacturing techniques for manufacturing multiple semiconductor package assemblies on a lead frame, as well as a semiconductor package assembly manufactured using this method. The method reduces the distances or intermediate spacings between singulated semiconductor packages on a lead frame to a width equal to the width of a cutting tool which width is significantly smaller than the distance required in any known modelling encapsulation technique. Therefore, the method according to the disclosure allows to position more semiconductor packages on a lead frame on one process step. Accordingly, as the number of semiconductor packages per lead frame surface is increased, more semiconductor packages can be manufactured and singulated in one process step, which reduces costs and processing time.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 4, 2024
    Applicant: NEXPERIA B.V.
    Inventors: Hiu Hay Nichole Lam, Shu-ming Yip, Chi Ho Leung, Shun Tik Yeung
  • Patent number: 10256168
    Abstract: A semiconductor device includes a semiconductor die having a first side having a first terminal and an opposite second side having at least two second terminals. A lead frame has a first part and a second part. The second part of the lead frame is both electrically and mechanically spaced from the first part. The second side of the die is attached to the lead frame such that the first and second lead frame parts are respectively connected to the at least two second terminals. The first and second lead frame parts include respective first and second extensions that project past a side of the die and provide first and second terminal surfaces that are co-planar with the first terminal on the first side of the die. The device makes use of the terminals on the both sides of the die. The device second side is exposed for thermal performance.
    Type: Grant
    Filed: June 12, 2016
    Date of Patent: April 9, 2019
    Assignee: Nexperia B.V.
    Inventors: Shun Tik Yeung, Pompeo V. Umali, Chi Ho Leung, Kan Wae Lam, Hans-Juergen Funke, Shu-Ming Yip
  • Publication number: 20170358514
    Abstract: A semiconductor device includes a semiconductor die having a first side having a first terminal and an opposite second side having at least two second terminals. A lead frame has a first part and a second part. The second part of the lead frame is both electrically and mechanically spaced from the first part. The second side of the die is attached to the lead frame such that the first and second lead frame parts are respectively connected to the at least two second terminals. The first and second lead frame parts include respective first and second extensions that project past a side of the die and provide first and second terminal surfaces that are co-planar with the first terminal on the first side of the die. The device makes use of the terminals on the both sides of the die. The device second side is exposed for thermal performance.
    Type: Application
    Filed: June 12, 2016
    Publication date: December 14, 2017
    Inventors: Shun Tik Yeung, Pompeo V. Umali, Chi Ho Leung, Kan Wae Lam, Hans-Juergen Funke, Shu-Ming Yip