Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; at least one second semiconductor layer of a second conductivity type formed in the first semiconductor layer to have an annular shape in plan view; an insulating layer formed on the first semiconductor layer; a first metal layer and a second metal layer formed on the insulating layer and spaced apart from each other; a second wiring layer provided in the insulating layer and configured to electrically connect an inner region of the first semiconductor layer surrounded by the at least one second semiconductor layer and the second metal layer; and a first wiring layer provided in the insulating layer and configured to electrically connect an outer region of the first semiconductor layer on the opposite side from the inner region with respect to the at least one second semiconductor layer and the first metal layer.

Abstract: A method of manufacturing a semiconductor device having a super junction structure, includes: forming a first-conductivity-type semiconductor layer having a first surface and a second surface opposite to the first surface; forming a second-conductivity-type pillar region in the semiconductor layer; forming an insulating layer which covers the second surface of the semiconductor layer; forming a metal layer on the insulating layer; forming a gate electrode including a first opening passing through the metal layer by selectively removing the metal layer; and etching the insulating layer via the first opening, wherein the etching the insulating layer includes partially exposing the semiconductor layer by forming a second opening having a curved sidewall in the insulating layer by isotropic etching, and wherein an exposed surface of the semiconductor layer forms a flat surface continuous with the second surface of the semiconductor layer covered with the insulating layer.

Abstract: A semiconductor device is provided with a semiconductor layer, which includes an active region and an outer peripheral region formed in a frame shape surrounding the active region and having rectangular outer peripheral edges. The outer peripheral region includes: a breakdown voltage structure region in which a breakdown voltage structure is formed; and a specific region extending from the outer peripheral edges of the outer peripheral region to an outer peripheral edge of the breakdown voltage structure region, and formed so that when viewed in a thickness direction of the semiconductor layer, the outer peripheral edge of the breakdown voltage structure region is recessed toward the active region. A contact region is formed on a front surface of the semiconductor layer in the specific region. A wiring electrically connected to the contact region is formed in an outermost peripheral region of the outer peripheral region.