Abstract: A method of forming a semiconductor device and the structure of the semiconductor device are provided. The manufacturing method includes the following steps of: providing a semiconductor substrate with a front side and a back side; forming a collector layer in the back side; conducting a first Hydrogen implant process to the back side to form an N-type region and baking the N-type region with a first annealing temperature to form a field stop buffer layer; conducting a second Hydrogen implant process to the back side to form a lifetime control site and baking the lifetime control site with a second annealing temperature to form a defect layer, wherein the second annealing temperature being lower than the first annealing temperature; and forming a metal layer on the back side.

Abstract: A method for fabricating integrated circuit devices, e.g., Flash memory devices, embedded Flash memory devices. The method includes providing a semiconductor substrate, e.g., silicon, silicon on insulator, epitaxial silicon. In a specific embodiment, the semiconductor substrate has a peripheral region and a cell region. The method includes forming a first dielectric layer (e.g., silicon dioxide) having a first thickness overlying a cell region and a second dielectric layer (e.g., silicon dixode) having a second thickness overlying the peripheral region. In a specific embodiment, the cell region is for Flash memory devices and/or other like structures. The method forms a pad oxide layer overlying the first dielectric layer and forms a nitride layer overlying the pad oxide layer.

Abstract: A method for fabricating integrated circuit devices, e.g., Flash memory devices, embedded Flash memory devices. The method includes providing a semiconductor substrate, e.g., silicon, silicon on insulator, epitaxial silicon. In a specific embodiment, the semiconductor substrate has a peripheral region and a cell region. The method includes forming a first dielectric layer (e.g., silicon dioxide) having a first thickness overlying a cell region and a second dielectric layer (e.g., silicon dixode) having a second thickness overlying the peripheral region. In a specific embodiment, the cell region is for Flash memory devices and/or other like structures. The method forms a pad oxide layer overlying the first dielectric layer and forms a nitride layer overlying the pad oxide layer.