Abstract: A method includes forming an interfacial layer over a substrate; forming a quasi-antiferroelectric (QAFE) layer over the interfacial layer, in which forming the QAFE layer comprises performing an atomic layer deposition (ALD) cycle, and the ALD cycle includes performing a first sub-cycle for X time(s), in which the first sub-cycle comprises providing a Zr-containing precursor; performing a second sub-cycle for Y time(s), in which the second sub-cycle comprises providing a Hf-containing precursor; and performing a third sub-cycle for Z time(s), in which the third sub-cycle comprises providing a Zr-containing precursor, and in which X+Z is at least three times Y; and forming a gate electrode over the QAFE layer.

Abstract: A method includes forming a semiconductor layer over a substrate; depositing a first ferroelectric layer over a channel region of the semiconductor layer; depositing a first dielectric layer over the first ferroelectric layer; depositing a second ferroelectric layer over the first dielectric layer; depositing a gate metal layer over the second ferroelectric layer; patterning the gate metal layer, the second ferroelectric layer, the first dielectric layer, and the first ferroelectric layer to form a gate structure; and forming source/drain regions in the semiconductor layer and on opposite sides of the gate structure.

Abstract: A semiconductor device includes a substrate, a gate structure over the substrate, and source/drain regions in the substrate and on opposite sides of the gate structure. The gate structure includes an interfacial layer, a quasi-antiferroelectric (QAFE) layer over the interfacial layer, and a gate electrode over the QAFE layer. The QAFE layer includes Hf1?xZrxO2, in which x is greater than 0.5 and is lower than 1.

Abstract: A method includes forming an interfacial layer over a substrate; forming a quasi-antiferroelectric (QAFE) layer over the interfacial layer, in which forming the QAFE layer comprises performing an atomic layer deposition (ALD) cycle, and the ALD cycle includes performing a first sub-cycle for X time(s), in which the first sub-cycle comprises providing a Zr-containing precursor; performing a second sub-cycle for Y time(s), in which the second sub-cycle comprises providing a Hf-containing precursor; and performing a third sub-cycle for Z time(s), in which the third sub-cycle comprises providing a Zr-containing precursor, and in which X+Z is at least three times Y; and forming a gate electrode over the QAFE layer.

Abstract: A Heterojunction with Intrinsic Thin layer (HIT) solar cell has a crystalline Si substrate, an intrinsic amorphous Si layer, a doped amorphous Si layer, a transparent conductive layer and two electrode layers. The intrinsic amorphous Si layer disposed between the doped amorphous Si layer and the crystalline silicon substrate contacts the doped amorphous Si layer and the crystalline silicon substrate. Each of the intrinsic amorphous Si layer and the doped amorphous Si layer has the thickness less than 50 nm. The intrinsic amorphous Si layer and the doped amorphous Si layer are both made by electron beam evaporation. The transparent conductive layer is formed on the doped amorphous Si layer. The two electrode layers are formed on the transparent conductive layer and the crystalline silicon substrate respectively. The crystalline silicon substrate is disposed between the two electrode layers.

Abstract: A method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices is disclosed. The method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices includes the following steps: (a) providing a substrate, (b) fixing the substrate, (c) applying a stress upon the substrate, and (d) inducing a strain in one of a device and a circuit by stressing the substrate.

Abstract: A MOSFET structure utilizing strained silicon carbon alloy and fabrication method thereof. The MOSFET structure includes a substrate, a graded SiGe layer, a relaxed buffer layer, a strained silicon carbon alloy channel layer, a gate dielectric layer, a polysilicon gate electrode (or metal gate electrode) and a source/drain region.

Abstract: A method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices is disclosed. The method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices includes the following steps: (a) providing a substrate, (b) fixing the substrate, (c) applying a stress upon the substrate, and (d) inducing a strain in one of a device and a circuit by stressing the substrate.

Abstract: A method for characterizing the quality of the interface between a silicon and a gate insulator in a MOS device includes the steps of: applying at least one current to the MOS device through the gate; detecting at least one electroluminescent signal corresponding to the silicon bandgap energy after the current flows through the MOS device; and outputting the electroluminescent waveform in the time domain. The quality of the interface between a silicon and a gate insulator in the MOS device is determined by analyzing the minority carrier lifetime in silicon. The invention also discloses a characterization system for implementing the method.

Abstract: An infrared photodetector formed of a MOS tunneling diode is disclosed. The infrared photodetector comprises a conducting layer, a semiconductor layer comprising at least one layer of quantum structure for confining a carrier in a barrier, an insulating layer formed between the conducting layer and the semiconductor layer, and a voltage source connected to the conducting layer and the semiconductor layer for providing a bias voltage to generate a quantum tunneling effect, such that the carrier penetrates through the insulating layer to form a current, wherein when irradiated by an infrared, the carrier in the barrier absorbs the energy of the infrared to jump out of the barrier and is collected by an electrode to form a photocurrent.

Abstract: Strained Si surrounding the SiGe embedded body on a SOI (silicon on insulator) substrate forms a novel FinFET. The mobility in the channel is enhanced due to strain of the Si channel. The strained Si FinFET includes a SOI substrate, an SiGe embedded body, a strained Si channel surrounding layer, an oxide layer, a poly Si gate electrode (or metal gate electrode), a source and a drain.

Abstract: A method for characterizing the quality of the interface between a silicon and a gate insulator in a MOS device includes the steps of: applying at least one current to the MOS device through the gate; detecting at least one electroluminescent signal corresponding to the silicon bandgap energy after the current flows through the MOS device; and outputting the electroluminescent waveform in the time domain. The quality of the interface between a silicon and a gate insulator in the MOS device is determined by analyzing the minority carrier lifetime in silicon. The invention also discloses a characterization system for implementing the method.