Patents by Inventor Shu Wei

Shu Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250053220
    Abstract: An electronic system is provided. The electronic system includes a processor and a first power management circuit. The processor generates and outputs a first data frame. The first data frame includes at least one first guard bit and a first address. The first power management circuit includes a first register. The first power management circuit receives the first data frame and determines legitimacy of the first address according to the least one first guard bit. In response to that the first address is legal, the power management circuit transmits a first response to the processor and accesses a first region in the first register according to the first address.
    Type: Application
    Filed: August 9, 2023
    Publication date: February 13, 2025
    Inventors: Kuan-Wen SU, Shu-Ching LIN, Chien-Yu LAN, Shang-Wei CHEN
  • Publication number: 20250054810
    Abstract: A semiconductor structure includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and including a conductive interconnect; and a cap layer disposed on the interconnect structure. The cap layer includes a cap portion disposed on the conductive interconnect. The cap portion includes a plurality of two-dimensional material sheets stacked on each other and has a lower surface proximate to the conductive interconnect. The lower surface of the cap portion is formed with a plurality of dangling bonds such that the cap portion is adhered to the conductive interconnect through the dangling bonds.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Wei LI, Hans HSU, Chien-Hsin HO, Yu-Chen CHAN, Blanka MAGYARI-KOPE, Shin-Yi YANG, Ming-Han LEE
  • Patent number: 12222576
    Abstract: An optical element driving mechanism includes a movable assembly, a fixed assembly, and a driving assembly. The movable assembly is configured to be connected to an optical element. The movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly in a range of motion. The optical element driving mechanism further includes a positioning assembly configured to position the movable assembly at a predetermined position relative to the fixed assembly when the driving assembly is not operating.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: February 11, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Kuen-Wang Tsai, Liang-Ting Ho, Chao-Hsi Wang, Chih-Wei Weng, He-Ling Chang, Che-Wei Chang, Sheng-Zong Chen, Ko-Lun Chao, Min-Hsiu Tsai, Shu-Shan Chen, Jungsuck Ryoo, Mao-Kuo Hsu, Guan-Yu Su
  • Publication number: 20250045316
    Abstract: An example method includes providing, to a sequence model (i) a plurality of few-shot prompts, wherein each prompt comprises a demonstration passage, a demonstration task, and a demonstration query, wherein the demonstration task describes a type of retrieval, and wherein the demonstration query is relevant to the demonstration task, and (ii) a plurality of passages sampled from a corpus of passages. The method also includes receiving, from the sequence model and for the plurality of passages and based on the plurality of few-shot prompts, a respective plurality of predicted task-query pairs, the sequence model having been prompted to predict a task based on an input passage, and predict an output query relevant to the predicted task. The method further includes generating a synthetic training dataset comprising the plurality of passages and the respective plurality of predicted task-query pairs. The method also includes providing the synthetic training dataset.
    Type: Application
    Filed: July 30, 2024
    Publication date: February 6, 2025
    Inventors: Jinhyuk Lee, Zhuyun Dai, Xiaoqi Ren, Iftekhar Naim, Yi Luan, Blair Yuxin Chen, Siddhartha Reddy Jonnalagadda, Ming-Wei Chang, Daniel Matthew Cer, Gustavo Adolfo Hernandez Abrego, Jeremy Robert Cole, Colin Hearne Evans, Yuzhe Zhao, Pranay Bhatia, Rajvi Kapadia, Riham Hassan Abdel-Moneim Mansour, Raphael Dominik Hoffman, Simon Kunio Tokumine, Scott Bradley Huffman, Stephen Zachary Karukas, Michael Yiupun Kwong, Shu Zheng, Yan Qiao, Lukas Rutishauser, Anand Rajan Iyer
  • Patent number: 12219843
    Abstract: An electronic device includes a conductive wire having a metal portion with openings. The openings include a first opening and a second opening arranged along a first direction, and the metal portion includes the first to fourth extending portions and the first to fourth joint portions. The first opening is surrounded by the first extending portion, the second extending portion, the first joint portion, and the second joint portion. The second opening is surrounded by the third extending portion, the fourth extending portion, the third joint portion, and the fourth joint portion. Along the first direction, a ratio of a first width sum of widths of the first extending portion, the second extending portion, the third extending portion, and the fourth extending portion to a second width sum of widths of the first joint portion and the third joint portion is in a range from 0.8 to 1.2.
    Type: Grant
    Filed: March 18, 2024
    Date of Patent: February 4, 2025
    Assignee: InnoLux Corporation
    Inventors: Ya-Wen Lin, Chien-Chih Chen, Yen-Hsi Tu, Cheng-Wei Chang, Shu-Hui Yang
  • Patent number: 12218130
    Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
  • Patent number: 12219693
    Abstract: A carrying structure is defined with a main area and a peripheral area adjacent to the main area, where a plurality of packaging substrates are disposed in the main area in an array manner, a plurality of positioning holes are disposed in the peripheral area, and a plurality of positioning traces are formed along a part of the edges of the plurality of positioning holes, such that the plurality of positioning traces are formed with notches.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: February 4, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chin-Wei Hsu, Jui-Kun Wang, Shu-Yu Ko, Fang-Wei Chang, Hsiu-Fang Chien
  • Publication number: 20250038960
    Abstract: An example may involve determining that a first proxy server is to share security credentials with a set of one or more proxy servers, wherein the set of one or more proxy servers is associated with the security credentials, and wherein the set of one or more proxy servers includes a second proxy server; transmitting, to the second proxy server, a request for the first proxy server to have access to the security credentials; and receiving, from the second proxy server, a credential key in an encrypted form, wherein the credential key is configured to decrypt the security credentials.
    Type: Application
    Filed: July 24, 2023
    Publication date: January 30, 2025
    Inventors: Jiayin Song, Matis Granger, Shu-Wei Hsu
  • Patent number: 12211740
    Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first dielectric layer and one or more first conductive features disposed in the first dielectric layer. The one or more first conductive features includes a first metal. The structure further includes a plurality of graphene layers disposed on each of the one or more first conductive features, the plurality of graphene layers include a second metal intercalated therebetween, and the second metal is different from the first metal.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 12204163
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: February 5, 2024
    Date of Patent: January 21, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20250016965
    Abstract: A method and a module for controlling a heat dissipation fan, and a non-transitory computer readable medium are provided, the module includes a BMC and a CPLD, the method includes: controlling the heat dissipation fan by the CPLD when the BMC stopped controlling the heat dissipation fan; obtaining a predetermined rotational speed and a predetermined control curve by the CPLD according to a status of the BMC and/or a status of the server; and detecting an environment temperature, obtaining a target rotational speed according to the environment temperature and the predetermined control curve, and controlling the heat dissipation fan to work with the target rotational speed by the CPLD, wherein the target rotational speed is less or equal to the predetermined rotational speed.
    Type: Application
    Filed: August 1, 2023
    Publication date: January 9, 2025
    Applicant: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: SHU-WEI ZHANG, NAN ZHANG
  • Publication number: 20240387699
    Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Shu-Wei Hsu, Yu-Jen Shen, Hao-Yun Cheng, Chih-Wei Wu, Ying-Tsung Chen, Ying-Ho Chen
  • Publication number: 20240387537
    Abstract: An IC driver includes a cascode arrangement of first-type transistors coupled in series with a cascode arrangement of second-type transistors different from the first-type transistors. Each cascode arrangement includes an active area extending in a first direction, gate structures extending perpendicular to the first direction and overlying the active area at locations corresponding to the transistors of the cascode arrangement, first through fourth metal segments extending in the first direction in a first metal layer of the IC, first and second vias electrically coupling respective first and second gate structures to the first and second metal segments, a third via electrically coupling a source terminal of the cascode arrangement to the third metal segment, and a fourth via electrically coupling a drain terminal of the cascode arrangement to the fourth metal segment. The third and fourth metal segments are aligned along the first direction.
    Type: Application
    Filed: May 15, 2023
    Publication date: November 21, 2024
    Inventors: Chia-Hui CHEN, Shu-Wei CHUNG, Kuei-Feng YEN, Chia-Jung CHANG
  • Publication number: 20240387518
    Abstract: A semiconductor device includes a substrate. A first nanosheet structure and a second nanosheet structure are disposed on the substrate. Each of the first and second nanosheet structures have at least one nanosheet forming source/drain regions and a gate structure including a conductive gate contact. A first oxide structure is disposed on the substrate between the first and second nanosheet structures. A conductive terminal is disposed in or on the first oxide structure. The conductive terminal, the first oxide structure and the gate structure of the first nanosheet structure define a capacitor.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chung-Hui Chen, Wan-Te Chen, Shu-Wei Chung, Tung-Heng Hsieh, Tzu-Ching Chang, Tsung-Hsin Yu, Yung Feng Chang
  • Publication number: 20240387251
    Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first dielectric layer and one or more first conductive features disposed in the first dielectric layer. The one or more first conductive features includes a first metal. The structure further includes a plurality of graphene layers disposed on each of the one or more first conductive features, the plurality of graphene layers include a second metal intercalated therebetween, and the second metal is different from the first metal.
    Type: Application
    Filed: July 27, 2024
    Publication date: November 21, 2024
    Inventors: Shu-Wei LI, Yu-Chen CHAN, Shin-Yi YANG, Ming-Han LEE, Shau-Lin SHUE
  • Publication number: 20240379558
    Abstract: An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, and the conductive layer includes one or more graphene layers. The first portion of the conductive layer includes a first interface portion and a second interface portion opposite the first interface portion, and each of the first and second interface portion includes a metal disposed between adjacent graphene layers. The structure further includes a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and the second portion of the conductive layer includes a third interface portion and a fourth interface portion opposite the third interface portion. Each of the third and fourth interface portion includes the metal disposed between adjacent graphene layers. The structure further includes a dielectric material disposed between the first and second portions of the conductive layer.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 14, 2024
    Inventors: Shu-Wei LI, Yu-Chen CHAN, Shin-Yi YANG, Ming-Han LEE, Shau-Lin SHUE
  • Publication number: 20240374963
    Abstract: An exercise device, endlessly pedaled by a user, includes a base unit, a training unit connected to the base unit, a detection unit arranged on the training unit, an analyzing and processing module coupled to the detection unit, and an electrical auxiliary unit coupled to the analyzing and processing module. The electrical auxiliary unit can assist in driving the training unit. The detection unit detects the usage state of the detection unit to generate a detection signal. When a user applies force to the training unit to exercise, the analyzing and processing module will determine that the assistance of external force is required according to the detection signal and transmit an electrical auxiliary signal to the electrical auxiliary unit if the exercise stagnates due to insufficient force. The electrical auxiliary unit assists in driving the training unit to help the user complete exercise according to the electrical auxiliary signal.
    Type: Application
    Filed: April 26, 2024
    Publication date: November 14, 2024
    Inventors: SHU-WEI CHANG, SHU-CHUN HUANG
  • Patent number: 12142312
    Abstract: A memory control circuit and a refresh method for a dynamic random access memory (DRAM) array are provided. The memory control circuit includes a mode register circuit, a command decoder and a refresh circuit. The mode register circuit includes a plurality of mode registers. The command decoder receives a refresh command and sets a flag of a target mode register corresponding to the refresh command among the plurality of mode registers to a setting value. The refresh circuit refreshes the DRAM array in response to the refresh command through the command decoder and the setting value of the flag of the target mode register.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: November 12, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shu-Wei Yang
  • Publication number: 20240367202
    Abstract: A process tool including a polishing pad on a top surface of a wafer platen. A wafer carrier is configured to hold a wafer over the polishing pad. A slurry dispenser is configured to dispense an abrasive slurry including a plurality of charged abrasive particles having a first polarity onto the polishing pad. A first conductive rod is within the wafer platen and coupled to a first voltage supply. A wafer roller is configured to support the wafer. A first wafer brush is arranged beside the wafer roller. A second conductive rod is within the first wafer brush and coupled to a second voltage supply. The first voltage supply is configured to apply a first charge having a second polarity, opposite the first polarity, to the first conductive rod. The second voltage supply is configured to apply a second charge having the second polarity to the second conductive rod.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Chih-Wen Liu, Yeo-Sin Lin, Shu-Wei Hsu, Che-Hao Tu, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 12136662
    Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Shu-Wei Hsu, Yu-Jen Shen, Hao-Yun Cheng, Chih-Wei Wu, Ying-Tsung Chen, Ying-Ho Chen