Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.

Abstract: A data strobe latching circuit and an adjusting method for adjusting an internal write latency signal are provided. The DQS latching circuit includes a receiver, a counting circuit and a timing adjusting circuit. The receiver receives a DQS signal. The counting circuit counts at least one pulse of the DQS signal to generate an adjusting value. The timing adjusting circuit adjusts a timing of the internal write latency signal according to the adjusting value.

Abstract: A system for self-seeding a bidirectional mode-locked laser includes a variable retroreflector optically coupled to an output port of the laser. In a first operating state, the variable retroreflector retroreflects output light from the output port back into the output port. In a second operating state, the variable retroreflector does not retroreflect the output light. To use the system, the laser is unidirectionally mode-locked to generate a first pulse train that exits the laser via a first output port. The variable retroreflector, in the first operating state, retroreflects output light from a second output port of the laser back into the laser to initiate bidirectional mode-locking. When the laser transitions to bidirectional mode-locking, this output light becomes a second pulse train. The variable retroreflector is then transitioned to the second operating state such that the second pulse train can be used for the application at hand.

Abstract: An array antenna module and a wireless communication device are provided, the array antenna module includes a dielectric substrate, at least one transmitting antenna and at least one receiving antenna arranged adjacent to each other and arranged on the dielectric substrate, and at least one decoupling element arranged on the dielectric substrate, at least a part of the decoupling element is arranged between the transmitting antenna and the receiving antenna; the decoupling element includes a first decoupling element and a second decoupling element, the first decoupling element is arranged closer to the transmitting antenna; the second decoupling element is arranged closer to the receiving antenna.

Abstract: An antenna testing device and system for testing an antenna array are provided, the antenna testing device includes a first dielectric substrate, a plurality of radiating units, a plurality of second dielectric substrates, and a plurality of power dividers. The first dielectric substrate includes a first area and a second area surrounding the first area. The radiating units are arranged in an array in a predetermined arrangement in the first area and the second area, which is corresponding to an arrangement of a plurality of antenna radiating units of the antenna array. The power dividers are arranged among the second dielectric substrates and connected to the radiating units arranged in the first area.

Abstract: Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N/P channel properties, provide a simple way to form the N/P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a substrate, a first semiconductor layer over the substrate, a second semiconductor layer over the first semiconductor layer and including a channel region sandwiched between a first source/drain region and a second source/drain region, a first plurality of nanostructures disposed over the channel region, a first leakage block layer over the first source/drain region, a second leakage block layer over the second source/drain region, a dielectric layer on the first leakage block layer, a first source/drain feature on the dielectric layer and in contact with first sidewalls of the first plurality of nanostructures, and a second source/drain feature disposed on the second leakage block layer and in contact with second sidewalls of the first plurality of nanostructures. The first leakage block layer and the second leakage block layer includes an undoped semiconductor material.

Abstract: A method for forming a semiconductor structure includes following operations. A hybrid layered structure is formed. The hybrid layered structure includes at least a 2D material layer and a first 3D material layer. Portions of the hybrid layered structure are removed to form a plurality of conductive features and at least an opening between the conductive features. A dielectric material is formed to fill the opening and to form an air gap sealed within.

Abstract: A piezoelectric speaker includes: a peripheral rectangular frame having four sides; a central rectangular frame disposed on the peripheral rectangular frame, wherein the central rectangular frame has four corners and four sides, and the four corners are connected to the four sides of the peripheral rectangular frame; four central triangular cantilevers disposed within the central rectangular frame, wherein each of the central triangular cantilevers has a vibrating end and a fixed end opposite to the vibrating end, and each of the fixed ends of the central triangular cantilevers is connected to the four sides of the central rectangular frame, the four vibrating ends of the four central triangular cantilevers are close to each other, and the four central triangular cantilevers have different dimensions of their respective areas defined within the central rectangular frame; and four peripheral triangular cantilevers disposed between the peripheral rectangular frame and the central rectangular frame.

Abstract: The invention provides a layout pattern cell of a static random access memory (SRAM), which at least comprises a first SRAM cell, a plurality of gate structures spanning a plurality of fin structures, so as to form a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first access transistor, a second access transistor, a third access transistor, a fourth access transistor, a first parasitic transistor and a second parasitic transistor located on a substrate, the first parasitic transistor and the first pull-down transistor span the same fin structure, and the fin structure spanned by the first parasitic transistor and the first pull-down transistor is a continuous structure.

Abstract: The present invention provides a piezoelectric speaker, including: a frame; a cantilever plate actuator disposed on the frame; a spring connected to the frame and the cantilever plate actuator; and a central diaphragm connected to the spring, wherein when the cantilever plate actuator vibrates, the central diaphragm vibrates with the spring.

Abstract: A structure including a conductive region, a dielectric region, and a capping layer is provided. The conductive region is disposed on or embedded in the dielectric region. The capping layer is disposed on the conductive region. A material of the capping layer includes a 2D material.

Abstract: In non-limiting examples of the present disclosure, systems, methods, and devices for matching device configurations to games are presented. A set of device configuration tiers may be generated from gameplay telemetry data generated by a plurality of client devices executing a plurality of games. A device configuration for a specific client device may be determined based at least on the specific client device's GUI type. When the specific client device accesses a software game library a determination may be made based on a performance tier corresponding to the device configuration for the specific client device as to whether the specific client device can adequately execute each game. One or more recommendations may be rendered and displayed in the game library based on the determination of whether the specific client device can adequately execute each game.

Abstract: A curable composition includes an epoxy monomer component and an aniline-based hardener. The epoxy monomer component is a first component formed from a first epoxy monomer represented by Formula (I), or a second component including the first epoxy monomer represented by Formula (I) and a second epoxy monomer different from the first epoxy monomer represented by Formula (I), wherein each of the substituents in Formula (I) is given the definitions as set forth in the Specification and Claims. Based on 100 wt % of the epoxy monomer component, an amount of the first epoxy monomer represented by Formula (I) is not smaller than 25 wt % and less than 100 wt % and an amount of the second epoxy monomer is greater than 0% and not greater than 75 wt %. A cured product formed from the curable composition, and a method for encapsulating a semiconductor device using the curable composition are also provided.

Abstract: An electrical connection device includes a mother board and a daughter board. The mother board includes a first board body with at least one cavity and a first electrical contact printed on the first board body. The daughter board includes a second board body and a second electrical contact printed on the second board body. At least one of the daughter board and the mother board includes at least one contour feature integrally formed with at least one of the first board body and the second board body. When the second board body is inserted into the at least one cavity of the first board body, the second electrical contact is electrically connected to the first electrical contact, and the daughter board is positioned in the mother board through the at least one contour feature.

Abstract: A thermal exchange device including a sliding plate and a thermal exchange unit is provided. The sliding plate includes a plate-shaped body, a first flange and a second flange. The first flange, protruding from a first side of the plate-shaped body, has a guide slit including a first section, a second section and a guide slit connecting the two sections. The first section, extending in a direction parallel to a long axis of the plate-shaped body, is separated from the first side by a first distance. The second section, extending to the said direction, is separated from the first side by a second distance greater than the first distance. The second flange, protruding from a second side of the plate-shaped body, defines a slide groove with the first flange and the plate-shaped body. The thermal exchange unit, at least partly received in the slide groove, includes a guide rod.

Abstract: An interconnect structure includes a conductive feature embedded in a dielectric feature. The conductive feature has a first horizontal portion and a first vertical portion. The first horizontal portion extends in a horizontal direction to terminate at two edge surfaces. The first horizontal portion includes graphene layers stacked on each other, and an intercalation material interposed among the graphene layers. The intercalation material includes a first atom dopant including one of a group 1 metal, a group 2 metal, a group 3 metal, a lanthanide series metal, an actinide series metal, and combinations thereof. The first vertical portion extends in a vertical direction and is in contact with one of the two edge surfaces of the first horizontal portion. The first vertical portion is made of a first electrically conductive metal material.

Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.

Abstract: A semiconductor structure includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and including a conductive interconnect; and a cap layer disposed on the interconnect structure. The cap layer includes a cap portion disposed on the conductive interconnect. The cap portion includes a plurality of two-dimensional material sheets stacked on each other and has a lower surface proximate to the conductive interconnect. The lower surface of the cap portion is formed with a plurality of dangling bonds such that the cap portion is adhered to the conductive interconnect through the dangling bonds.