Patents by Inventor Shu-Wei Chu

Shu-Wei Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230215902
    Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.
    Type: Application
    Filed: March 15, 2023
    Publication date: July 6, 2023
    Inventors: Yun-Chung Na, Che-Fu Liang, Shu-Lu Chen, Szu-Lin Cheng, Han-Din Liu, Chien-Lung Chen, Yuan-Fu Lyu, Chieh-Ting Lin, Bo-Jiun Chen, Hui-Wen Chen, Shu-Wei Chu, Chung-Chih Lin, Kuan-Chen Chu
  • Patent number: 11637142
    Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: April 25, 2023
    Assignee: Artilux, Inc.
    Inventors: Yun-Chung Na, Che-Fu Liang, Shu-Lu Chen, Szu-Lin Cheng, Han-Din Liu, Chien-Lung Chen, Yuan-Fu Lyu, Chieh-Ting Lin, Bo-Jiun Chen, Hui-Wen Chen, Shu-Wei Chu, Chung-Chih Lin, Kuan-Chen Chu
  • Patent number: 10835603
    Abstract: A method for normalizing blood vessels of lesions is disclosed, which includes administering an effective amount of oxygen-loaded microbubbles to a subject in need by intravenous injection, and projecting ultrasound from a ultrasonic emission device into the lesions for rupturing the oxygen-loaded microbubbles and releasing the oxygen to the lesions. Each of the oxygen-loaded microbubbles comprises oxygen and a water insoluble gas, and the particle size of microbubbles is 0.5˜20 ?m.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: November 17, 2020
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chih-Kuang Yeh, Yi-Ju Ho, Shu-Wei Chu
  • Publication number: 20190365895
    Abstract: A method for normalizing blood vessels of lesions is disclosed, which includes administering an effective amount of oxygen-loaded microbubbles to a subject in need by intravenous injection, and projecting ultrasound from a ultrasonic emission device into the lesions for rupturing the oxygen-loaded microbubbles and releasing the oxygen to the lesions. Each of the oxygen-loaded microbubbles comprises oxygen and a water insoluble gas, and the particle size of microbubbles is 0.5˜20 ?m.
    Type: Application
    Filed: November 21, 2018
    Publication date: December 5, 2019
    Inventors: Chih-Kuang YEH, Yi-Ju HO, Shu-Wei CHU
  • Publication number: 20190348463
    Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Inventors: Yun-Chung Na, Che-Fu Liang, Shu-Lu Chen, Szu-Lin Cheng, Han-Din Liu, Chien-Lung Chen, Yuan-Fu Lyu, Chieh-Ting Lin, Bo-Jiun Chen, Hui-Wen Chen, Shu-Wei Chu, Chung-Chih Lin, Kuan-Chen Chu
  • Patent number: 10418407
    Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: September 17, 2019
    Assignee: Artilux, Inc.
    Inventors: Yun-Chung Na, Che-Fu Liang, Shu-Lu Chen, Szu-Lin Cheng, Han-Din Liu, Chien-Lung Chen, Yuan-Fu Lyu, Chieh-Ting Lin, Bo-Jiun Chen, Hui-Wen Chen, Shu-Wei Chu, Chung-Chih Lin, Kuan-Chen Chu
  • Publication number: 20180247968
    Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.
    Type: Application
    Filed: April 3, 2018
    Publication date: August 30, 2018
    Inventors: Yun-Chung Na, Che-Fu Liang, Shu-Lu Chen, Szu-Lin Cheng, Han-Din Liu, Chien-Lung Chen, Yuan-Fu Lyu, Chieh-Ting Lin, Bo-Jiun Chen, Hui-Wen Chen, Shu-Wei Chu, Chung-Chih Lin, Kuan-Chen Chu
  • Patent number: 9385740
    Abstract: A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: July 5, 2016
    Assignee: MEDIATEK INC.
    Inventors: Chi Yun Wang, Jen-Che Tsai, Shu-Wei Chu
  • Publication number: 20160134300
    Abstract: A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase.
    Type: Application
    Filed: October 22, 2015
    Publication date: May 12, 2016
    Inventors: Chi Yun Wang, Jen-Che Tsai, SHU-WEI CHU
  • Patent number: 8988120
    Abstract: A frequency multiplier includes a first impedance module, a second impedance module, a first path and a second path. When the first path is conducted, the first impedance module generates a first output signal and the second impedance module generates a second output signal. When the second path is conducted, the first impedance module generates a third output signal and the second impedance module generates a fourth output signal. The first and second paths are not conducted simultaneously. A frequency of a first combination signal generated from the first and third output signals and a frequency of a second combination signal generated from the second and fourth output signals are N times of a frequency of the input signal, where N is a positive rational number.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: March 24, 2015
    Assignee: MStar Semiconductor, Inc.
    Inventors: Shu-Wei Chu, Yao-Chi Wang
  • Publication number: 20140184282
    Abstract: A frequency multiplier includes a first impedance module, a second impedance module, a first path and a second path. When the first path is conducted, the first impedance module generates a first output signal and the second impedance module generates a second output signal. When the second path is conducted, the first impedance module generates a third output signal and the second impedance module generates a fourth output signal. The first and second paths are not conducted simultaneously. A frequency of a first combination signal generated from the first and third output signals and a frequency of a second combination signal generated from the second and fourth output signals are N times of a frequency of the input signal, where N is a positive rational number.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 3, 2014
    Applicant: MStar Semiconductor, Inc.
    Inventors: Shu-Wei Chu, Yao-Chi Wang
  • Patent number: 8669558
    Abstract: A pixel structure includes a thin film transistor device, an insulating layer disposed on the thin film transistor device, and a pixel electrode disposed on the insulating layer. The thin film transistor device includes a floating conductive pad disposed at one side of a semiconductor layer, and electrically connected to a source/drain electrode. The insulating layer has a first contact hole partially exposing the floating conductive pad. The pixel electrode is electrically connected to the floating conductive pad via the first contact hole.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: March 11, 2014
    Assignee: AU Optronics Corp.
    Inventors: Ching-Yang Liu, Wei-Hsiang Lin, Shu-Wei Chu, Hsiang-Chih Hsiao, Jhih-Jie Huang, Sai-Chang Liu, Yu-Hsing Liang
  • Publication number: 20120292622
    Abstract: A pixel structure includes a thin film transistor device, an insulating layer disposed on the thin film transistor device, and a pixel electrode disposed on the insulating layer. The thin film transistor device includes a floating conductive pad disposed at one side of a semiconductor layer, and electrically connected to a source/drain electrode. The insulating layer has a first contact hole partially exposing the floating conductive pad. The pixel electrode is electrically connected to the floating conductive pad via the first contact hole.
    Type: Application
    Filed: January 12, 2012
    Publication date: November 22, 2012
    Inventors: Ching-Yang Liu, Wei-Hsiang Lin, Shu-Wei Chu, Hsiang-Chih Hsiao, Jhih-Jie Huang, Sai-Chang Liu, Yu-Hsing Liang