Patents by Inventor Shu Yi Ying
Shu Yi Ying has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240386180Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
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Patent number: 11714947Abstract: A method of manufacturing an integrated circuit includes adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first and second pair of conductive patterns on the corresponding first and second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and a second set of conductive structures based on the second pair of conductive patterns. A first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. One spacing of a first set of spacings is different from another spacing of the first set of spacings.Type: GrantFiled: May 20, 2022Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mahantesh Hanchinal, Shu-Yi Ying, Chi Wei Hu, Min-Yuan Tsai
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Publication number: 20230237237Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.Type: ApplicationFiled: March 27, 2023Publication date: July 27, 2023Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Mohammed Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
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Patent number: 11615227Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.Type: GrantFiled: December 21, 2020Date of Patent: March 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
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Publication number: 20220284165Abstract: A method of manufacturing an integrated circuit includes adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first and second pair of conductive patterns on the corresponding first and second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and a second set of conductive structures based on the second pair of conductive patterns. A first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. One spacing of a first set of spacings is different from another spacing of the first set of spacings.Type: ApplicationFiled: May 20, 2022Publication date: September 8, 2022Inventors: Mahantesh HANCHINAL, Shu-Yi YING, Chi Wei HU, Min-Yuan TSAI
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Patent number: 11341308Abstract: A method of manufacturing an integrated circuit includes generating a layout of a first and a second cell, adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first pair of conductive patterns on the first set of routing tracks, placing a second pair of conductive patterns on the second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and forming a second set of conductive structures based on the second pair of conductive patterns. The first and second cell have a same cell height that is a non-integer multiple of a minimum pitch.Type: GrantFiled: February 18, 2021Date of Patent: May 24, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mahantesh Hanchinal, Shu-Yi Ying, Chi Wei Hu, Min-Yuan Tsai
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METHOD OF GENERATING LAYOUT DIAGRAM INCLUDING DUMMY PATTERN CONVERSION AND SYSTEM OF GENERATING SAME
Publication number: 20210374317Abstract: A method (of revising an initial layout diagram of a wire routing arrangement, the initial layout diagram and versions thereof being stored on a non-transitory computer-readable medium) includes identifying, in a first conductance layer of the initial layout diagram, a routed pattern and a dummy pattern, each of which extends in a first direction and revising to form a revised layout diagram. The routed patterns are functional in a representation of a circuit and the dummy patterns are non-functional in the representation of the circuit. The revising includes connecting first ends of the corresponding routed and dummy patterns and connecting second ends of the corresponding routed and dummy patterns.Type: ApplicationFiled: August 6, 2021Publication date: December 2, 2021Inventors: Ritesh KUMAR, Hiranmay BISWAS, Shu-Yi YING, Kuo-Nan YANG, Chung-Hsing WANG -
Method of generating layout diagram including dummy pattern conversion and system of generating same
Patent number: 11087063Abstract: A method (of revising an initial layout diagram of a wire routing arrangement) includes: identifying, in a first conductance layer of the initial layout diagram, a routed pattern and a dummy pattern, each of which extends in a first direction; the routed patterns being functional in a representation of a circuit; the dummy patterns being non-functional in the representation of the circuit; and revising to form a revised layout diagram, the revising including adding first and second jumper patterns, into a second conductance layer, which extend in a second direction substantially perpendicular to the first direction, and adding via patterns, into an interconnection layer between the first and second conductance layers, which represent (A) connections between the first jumper pattern and first ends of the corresponding routed and dummy patterns, and (B) connections between the second jumper pattern and second ends of the corresponding routed and dummy patterns.Type: GrantFiled: May 7, 2019Date of Patent: August 10, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ritesh Kumar, Chung-Hsing Wang, Kuo-Nan Yang, Hiranmay Biswas, Shu-Yi Ying -
Publication number: 20210173996Abstract: A method of manufacturing an integrated circuit includes generating a layout of a first and a second cell, adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first pair of conductive patterns on the first set of routing tracks, placing a second pair of conductive patterns on the second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and forming a second set of conductive structures based on the second pair of conductive patterns. The first and second cell have a same cell height that is a non-integer multiple of a minimum pitch.Type: ApplicationFiled: February 18, 2021Publication date: June 10, 2021Inventors: Mahantesh HANCHINAL, Shu-Yi YING, Chi Wei HU, Min-Yuan TSAI
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Publication number: 20210117605Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.Type: ApplicationFiled: December 21, 2020Publication date: April 22, 2021Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Mohammed Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
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Patent number: 10936780Abstract: A method of manufacturing an integrated circuit includes identifying a first cell of a layout, placing a first pair of conductive patterns on a first set of routing tracks, placing a second pair of conductive patterns on a second set of routing tracks, and forming, by a first mask, a first set of conductive structures based on the first pair or second pair of conductive patterns. The first cell abuts a second cell. The first cell has a first set of routing tracks. The second cell has a second set of routing tracks. The first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. A top and bottom boundary of the first cell overlaps a pair of the first set of routing tracks. A top and bottom boundary of the second cell overlaps a pair of the second set of routing tracks.Type: GrantFiled: August 30, 2019Date of Patent: March 2, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mahantesh Hanchinal, Chi Wei Hu, Min-Yuan Tsai, Shu-Yi Ying
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Patent number: 10872190Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.Type: GrantFiled: January 31, 2019Date of Patent: December 22, 2020Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
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Publication number: 20200019666Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.Type: ApplicationFiled: January 31, 2019Publication date: January 16, 2020Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
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METHOD OF GENERATING LAYOUT DIAGRAM INCLUDING DUMMY PATTERN CONVERSION AND SYSTEM OF GENERATING SAME
Publication number: 20200004915Abstract: A method (of revising an initial layout diagram of a wire routing arrangement) includes: identifying, in a first conductance layer of the initial layout diagram, a routed pattern and a dummy pattern, each of which extends in a first direction; the routed patterns being functional in a representation of a circuit; the dummy patterns being non-functional in the representation of the circuit; and revising to form a revised layout diagram, the revising including adding first and second jumper patterns, into a second conductance layer, which extend in a second direction substantially perpendicular to the first direction, and adding via patterns, into an interconnection layer between the first and second conductance layers, which represent (A) connections between the first jumper pattern and first ends of the corresponding routed and dummy patterns, and (B) connections between the second jumper pattern and second ends of the corresponding routed and dummy patterns.Type: ApplicationFiled: May 7, 2019Publication date: January 2, 2020Inventors: Ritesh KUMAR, Chung-Hsing WANG, Kuo-Nan YANG, Hiranmay BISWAS, Shu-Yi YING -
Publication number: 20190392108Abstract: A method of manufacturing an integrated circuit includes identifying a first cell of a layout, placing a first pair of conductive patterns on a first set of routing tracks, placing a second pair of conductive patterns on a second set of routing tracks, and forming, by a first mask, a first set of conductive structures based on the first pair or second pair of conductive patterns. The first cell abuts a second cell. The first cell has a first set of routing tracks. The second cell has a second set of routing tracks. The first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. A top and bottom boundary of the first cell overlaps a pair of the first set of routing tracks. A top and bottom boundary of the second cell overlaps a pair of the second set of routing tracks.Type: ApplicationFiled: August 30, 2019Publication date: December 26, 2019Inventors: Mahantesh HANCHINAL, Chi Wei HU, Min-Yuan TSAI, Shu-Yi YING
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Patent number: 10402529Abstract: A method of designing a layout includes identifying a cell having a cell height being a non-integral multiple of a minimum pitch, generating, using a processor, possibilities of an ordered arrangement of a plurality of virtual grid lines parallel to the top boundary and the bottom boundary, and placing at least two conductive patterns on the plurality of virtual grid lines. The cell height is defined by a top boundary and a bottom boundary, and the minimum pitch is based on a manufacturing process. The plurality of virtual grid lines are separated from each other by a plurality of spacings, and the top boundary overlaps a first virtual grid line of the plurality of virtual grid lines and the bottom boundary overlaps a second virtual grid line of the plurality of virtual grid lines. At least one spacing is different from another spacing of the plurality of spacings.Type: GrantFiled: November 18, 2016Date of Patent: September 3, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mahantesh Hanchinal, Chi Wei Hu, Min-Yuan Tsai, Shu-Yi Ying
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Patent number: 10331838Abstract: A layout method is disclosed that includes: placing function cells in a layout, corresponding to at least one design file, of an integrated circuit; and inserting at least one fill cell that is configured without cut pattern to fill at least one empty region between the function cells each comprising at least one cut pattern on at least one edge abutting the at least one empty region.Type: GrantFiled: July 26, 2017Date of Patent: June 25, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chan Yang, Hui-Zhong Zhuang, Ting-Wei Chiang, Yun-Xiang Lin, Tien-Yu Kuo, Shu-Yi Ying
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Publication number: 20180165399Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.Type: ApplicationFiled: July 26, 2017Publication date: June 14, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chan YANG, Hui-Zhong ZHUANG, Ting-Wei CHIANG, Yun-Xiang LIN, Tien-Yu KUO, Shu-Yi YING
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Publication number: 20180144082Abstract: A method of designing a layout includes identifying a cell having a cell height being a non-integral multiple of a minimum pitch, generating, using a processor, possibilities of an ordered arrangement of a plurality of virtual grid lines parallel to the top boundary and the bottom boundary, and placing at least two conductive patterns on the plurality of virtual grid lines. The cell height is defined by a top boundary and a bottom boundary, and the minimum pitch is based on a manufacturing process. The plurality of virtual grid lines are separated from each other by a plurality of spacings, and the top boundary overlaps a first virtual grid line of the plurality of virtual grid lines and the bottom boundary overlaps a second virtual grid line of the plurality of virtual grid lines. At least one spacing is different from another spacing of the plurality of spacings.Type: ApplicationFiled: November 18, 2016Publication date: May 24, 2018Inventors: Mahantesh HANCHINAL, Chi Wei HU, Min-Yuan TSAI, Shu-Yi YING
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Patent number: 9672315Abstract: An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.Type: GrantFiled: July 29, 2010Date of Patent: June 6, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Yi-Kan Cheng, Chung-Hsing Wang, Chen-Fu “Alex” Huang, Hsiao-Shu Chao, Chin-Yu Chiang, Ho Che Yu, Chih Sheng Tsai, Shu Yi Ying