Patents by Inventor Shu Zhou
Shu Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11976093Abstract: The disclosure discloses an ultrasonic-assisted pretreatment method for extraction of multiple steroid hormones in a sediment, including the following steps: (1) lyophilizing the sediment, grinding the sediment, and passing the ground sediment through a 40-60-mesh sieve; (2) placing the sample obtained in step (1) in a container; (3) adding an extractant to the container in step (2), shaking the mixture for 15 s-30 s, centrifuging the mixture to collect an supernatant after ultrasonication, and repeating extraction three times; where the extractants used in the three times of extraction are two of methanol, acetonitrile and acetone; and (4) after mixing the supernatants of the three times of extraction obtained in step (3), concentrating the mixture under a nitrogen flow at 20-30° C., passing the concentrated mixture through a filter, and performing detection. By using the method of the disclosure, the maximum recovery can be up to 100%.Type: GrantFiled: February 9, 2021Date of Patent: May 7, 2024Assignee: JIANGNAN UNIVERSITYInventors: Hua Zou, Xin Luo, Ruihua Dai, Yun Zhang, Shu Shu, Zhengkai Zhou
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Publication number: 20240140023Abstract: The present disclosure provides a method for photo-curing 4D printing of a multi-layer structure with an adjustable shape recovery speed, and a multi-layer structure printed thereby. The multi-layer structure printed by the method for photo-curing 4D printing of the multi-layer structure with the adjustable shape recovery speed includes a plurality of deformation units sequentially connected in series, and each of the plurality of the deformation units includes two slow layers, a fast layer, and a transition layer; and the fast layer is arranged between the two slow layers, and the transition layer is arranged between at least one of the two slow layers and the fast layer. In the present disclosure, a low cross-linking layer is doped with a nanocarbon light-absorbing material to solve the problem that the low cross-linking layer is prone to over-curing when a high cross-linking layer is printed on the low cross-linking layer.Type: ApplicationFiled: December 16, 2022Publication date: May 2, 2024Applicant: Jiangsu UniversityInventors: Shu HUANG, Hang ZHANG, Jianzhong ZHOU, Jie SHENG, Jiean WEI, Hongwei YANG, Cheng WANG, Mingyuan SHAN
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Publication number: 20240086685Abstract: A method, apparatus, device and storage medium for recommending information. The method includes determining, based on a set of feature representations of a plurality of features associated with information recommendation, a first set of weights indicating importance of the plurality of features. The method also includes determining a second set of weights based on the set of feature representations and the first set of weights. The method further includes recommending the information to a user based on the set of feature representations, the first set of weights and the second set of weights. The importance of respective features associated with the information recommendation can be accurately determined through this method, which further improves the effectiveness of information recommendation and improves the user experience.Type: ApplicationFiled: September 8, 2023Publication date: March 14, 2024Inventors: Xiaosong ZHOU, Qingliang CAI, Shu CHEN, Zhe WANG, Haiqian HE
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Publication number: 20240049450Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Gregory GEORGE, Akash GARG, Allen B. GARDINER, Shem OGADHOH, Juan G. ALZATE VINASCO, Umut ARSLAN, Fatih HAMZAOGLU, Nikhil MEHTA, Jared STOEGER, Yu-Wen HUANG, Shu ZHOU
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Publication number: 20240026513Abstract: The present invention relates to a pre-coated steel sheet with aluminum or aluminum alloy pre-coating, manufacturing method and hot stamped components. In the present invention, the method for manufacturing a pre-coated steel sheet with aluminum or aluminum alloy pre-coating relates to the situation of 0.10%?C0?0.30%, the dew point of the mixed atmosphere is controlled in the range of ?40˜?15° C. As for the situation of 0.30%<C0?0.50%, the dew point of the mixed atmosphere is controlled in the range of ?36˜?12° C. The present invention also discloses a pre-coated steel sheet with aluminum or aluminum alloy pre-coating obtained by the method and a hot stamping components obtained by the pre-coated steel sheet. The improved toughness and VDA peak force are achieved for the hot stamping components and then the collision safety of hot stamping components is elevated.Type: ApplicationFiled: October 28, 2020Publication date: January 25, 2024Applicant: IRONOVATION MATERIALS TECHNOLOGY CO., LTD.Inventors: Hongliang YI, Shu ZHOU, Zeran HOU, Xiaochuan XIONG
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Patent number: 11832438Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.Type: GrantFiled: June 28, 2019Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Jared Stoeger, Yu-Wen Huang, Shu Zhou
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Publication number: 20230369501Abstract: Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Applicant: Intel CorporationInventors: Cheng Tan, Yu-Wen Huang, Hui-Min Chuang, Xiaojun Weng, Nikhil J. Mehta, Allen B. Gardiner, Shu Zhou, Timothy Jen, Abhishek Anil Sharma, Van H. Le, Travis W. Lajoie, Bernhard Sell
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Publication number: 20230235439Abstract: The present invention relates to a coated steel sheet having a thin aluminium alloy coating and a coating method thereof The coated steel sheet of the present invention is used for hot stamping. The coating thickness of the coated steel sheet is 5˜14 ?m, wherein the aluminium alloy coating comprises a FeAlSi inhibitive layer adjacent to a substrate steel sheet and an Al alloy layer outside the FeAlSi inhibitive layer, wherein the thickness of the FeAlSi inhibitive layer is no more than 60% of the coating thickness and is 1.5˜6.0 ?m. The diameters of Kirkendall voids within 2 ?m from an interface between the FeAlSi inhibitive layer and the substrate steel to the interior of the substrate steel are no more than 2.5 ?m, wherein the number of Kirkendall voids with a diameter of no less than 0.5 ?m and no more than 2.5 ?m does not exceed 15 per 35 ?m. The present invention also discloses a coating method for coating a thin aluminium alloy coating on a substrate steel sheet for hot stamping.Type: ApplicationFiled: July 20, 2020Publication date: July 27, 2023Applicant: IRONOVATION MATERIALS TECHNOLOGY CO., LTD.Inventors: Hongliang YI, Shu ZHOU, Xiaochuan XIONG
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Publication number: 20230200043Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.Type: ApplicationFiled: February 14, 2023Publication date: June 22, 2023Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Gregory GEORGE, Akash GARG, Julie ROLLINS, Allen B. GARDINER, Shem OGADHOH, Juan G. ALZATE VINASCO, Umut ARSLAN, Fatih HAMZAOGLU, Nikhil MEHTA, Yu-Wen HUANG, Shu ZHOU
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Patent number: 11610894Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.Type: GrantFiled: June 28, 2019Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Julie Rollins, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Yu-Wen Huang, Shu Zhou
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Patent number: 11594637Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.Type: GrantFiled: March 27, 2020Date of Patent: February 28, 2023Assignee: Intel CorporationInventors: Leonard P. Guler, Stephen Snyder, Biswajeet Guha, William Hsu, Urusa Alaan, Tahir Ghani, Michael K. Harper, Vivek Thirtha, Shu Zhou, Nitesh Kumar
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Patent number: 11569370Abstract: An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.Type: GrantFiled: June 27, 2019Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Leonard P. Guler, Vivek Thirtha, Shu Zhou, Nitesh Kumar, Biswajeet Guha, William Hsu, Dax Crum, Oleg Golonzka, Tahir Ghani, Christopher Kenyon
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Method of contact patterning of thin film transistors for embedded DRAM using a multi-layer hardmask
Patent number: 11563107Abstract: An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).Type: GrantFiled: March 22, 2019Date of Patent: January 24, 2023Assignee: Intel CorporationInventors: Chieh-Jen Ku, Bernhard Sell, Pei-Hua Wang, Nikhil Mehta, Shu Zhou, Jared Stoeger, Allen B. Gardiner, Akash Garg, Shem Ogadhoh, Vinaykumar Hadagali, Travis W. Lajoie -
Patent number: 11519046Abstract: A cold-rolled high-strength steel plate having excellent phosphating performance and formability and a manufacturing method therefor. The chemical composition of the steel plate is, in percentage by weight, C 0.01-0.20%, Si 1.50-2.50%, Mn 1.50-2.50%, P?0.02%, S?0.02%, Al 0.03-0.06%, N?0.01%, the remainder being Fe and impurities. The surface layer of the steel plate has an inner oxide layer with a thickness of 1-5 ?m, and there is no enrichment of Si and Mn on the surface of the steel plate. The steel plate has tensile strength of ?980 MPa and an elongation of ?20%. The structure at the room temperature contains retained austenite, ferrite, and martensite and/or bainite.Type: GrantFiled: August 29, 2017Date of Patent: December 6, 2022Assignee: BAOSHAN IRON & STEEL CO., LTD.Inventors: Shu Zhou, Yong Zhong, Xinyan Jin, Li Wang
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Patent number: 11505844Abstract: A cold-rolled steel plate (1) and a manufacturing method therefor. The chemical composition of the steel plate (1) in percentage by weight is: C 0.15-0.25%, Si 1.50-2.50%, Mn 2.00-3.00%, P?0.02%, S?0.01%, Al 0.03-0.06%, N?0.01%, with the balance being Fe and impurities. The surface layer has an inner oxide layer (2) with a thickness of 1-5 ?m, and there is no enrichment of Si or Mn on the surface. The steel plate (1) has good phosphating performance and formability, with a tensile strength of ?1180 MPa and an elongation of ?14%, and has a complex-phase structure of ferrite, martensite, and retained austenite, the content of the retained austenite being not lower than 5%. A dew point is at ?25° C. to 10° C. in continuous annealing, such that external oxidation transitions to internal oxidation.Type: GrantFiled: August 29, 2017Date of Patent: November 22, 2022Assignee: BAOSHAN IRON & STEEL CO., LTD.Inventors: Shu Zhou, Yong Zhong, Xinyan Jin, Li Wang
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Publication number: 20220325944Abstract: The present application belongs to the technical field of intelligent household appliances, and relates to a prompt method for a refrigerator. The method comprises establishing a dish database according to the menu query information of the user, wherein the dish database comprises dishes and foods corresponding to the dishes; establishing a food database according to each food in the refrigerator and the time when the food enters the refrigerator; detecting food in the current refrigerator, wherein each food in the refrigerator is matched with a corresponding dish according to a dish database, and prompt information is obtained according to the time when the food enters the refrigerator in the food database; and prompting with the prompt information; wherein the prompt information includes expected expiration times and recommended dishes.Type: ApplicationFiled: November 12, 2020Publication date: October 13, 2022Inventors: Jian WU, Shu ZHOU, Zhiqun FENG, Zhaojun FEI, Zuowei YI
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Publication number: 20220326698Abstract: The present application belongs to the technical field of smart appliances, and relates to a delivery control method, which comprises the steps of: transferring goods to a delivery device according to the number of personnel; and controlling the delivery device to move to a set target position. By adopting the method, the corresponding quantity of goods can be configured based on the number of personnel, and moved to the target position by the delivery device, so that the required quantity of goods can be distributed to the target position without requiring a user to give control instructions, thereby providing convenience for the user; meanwhile, the required quantity can be distributed at a time, thereby improving the distribution efficiency and improving the user experience. The present application further discloses a delivery control device and a delivery device.Type: ApplicationFiled: November 5, 2020Publication date: October 13, 2022Inventors: Jian WU, Shu ZHOU, Zuowei YI, Zhaojun FEI, Zhiqun FENG
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Publication number: 20220321963Abstract: The present disclosure relates to the technical field of big data analysis, and discloses a method for video recommendation. The method includes: determining a first reference video according to a watching history of a user; determining a collection of recommended videos according to the first reference video; selecting a second reference video from the collection of recommended videos, where videos not selected in the collection of recommended videos are used as candidate videos; and determining recommended videos according to the similarity between the candidate videos and the second reference video. According to the method, a collection of recommended videos is determined according to a watching history of a user, reference videos are selected from the collection of recommended videos, and then recommended videos are determined according to the reference videos, so that the recommended videos are more customized and targeting, matching user requirements and enabling a better user experience.Type: ApplicationFiled: November 12, 2020Publication date: October 6, 2022Inventors: Jian WU, Shu ZHOU, Zhaojun FEI, Zuowei YI, Chunhui JIANG, Zhiqun FENG
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Publication number: 20220251673Abstract: Provided in the present disclosure is a method of heat treating a high-strength steel, wherein the high-strength steel comprises, by weight: 0.30-0.45% C, 1.0% or less Si, 0.20-2.5% Mn, 0.20-2.0% Cr, 0.15-0.50% Mo, 0.10-0.40% V, 0.2% or less Ti, 0.2% or less Nb, and a balance of Fe and other alloy elements and impurities, wherein the above alloy elements make Eq(Mn) according to the following formula (1) no less than 1.82, which method comprises the steps of 1) austenitizing; 2) carbide precipitation; and 3) tempering. The heat-treated steel in accordance with the present invention has high strength, high ductility and high toughness at the same time, especially improved reduction in area of tensile sample, so that it is particularly suitable for preparing spring members for vehicle suspension. Eq(Mn)=Mn+0.26Si+3.50P+1.30Cr+2.Type: ApplicationFiled: October 18, 2019Publication date: August 11, 2022Applicant: IRONOVATION MATERIALS TECHNOLOGY CO., LTD.Inventors: Hongliang YI, Shu ZHOU, Dapeng YANG, Huajie QIN, Xiaochuan XIONG, Guodong WANG
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Patent number: D1004630Type: GrantFiled: March 10, 2023Date of Patent: November 14, 2023Inventor: Shu Zhou