Abstract: An intra prediction method and device and a computer-readable storage medium, the method comprising: configuring actual angle modes indicated by relative angle numbers, wherein the relative angle numbers are successively represented within a prediction direction range corresponding to a preset width and height relationship; starting from a starting angle, using a corresponding actual angle mode after sampling preset angle sample points, said starting angle being determined according to the width and height relationship of processing blocks and the prediction direction range corresponding to the preset width and height relationship, and actual angles having a one-to-one correspondence with the actual angle modes.

Abstract: A method for intra prediction includes: obtaining multiple previously reconstructed neighbouring blocks corresponding to a current processing block; determining prediction modes, that are signalled in a bitstream, corresponding to neighbouring blocks of the multiple previously reconstructed neighbouring blocks, to obtain multiple first prediction modes; if the multiple first prediction modes comprise at least two directional modes, taking directional modes comprised in the multiple first prediction modes as first prediction directions; performing, according to a preset operation rule, operation on multiple first prediction directions of the first prediction directions to obtain second prediction directions; obtaining a prediction mode set according to the second prediction directions and the multiple first prediction modes; and performing intra prediction on the current processing block based on the prediction mode set.

Abstract: A dynamic power control method and system for resisting multi-user parameter biased aggregation in federated learning are provided; the method includes: (1) establishing a federated learning system model for resisting parameter biased aggregation; (2) constructing a 5 corresponding objective function based on a training purpose of the federated learning system model; (3) introducing, according to the established federated learning system model, a power control factor for resisting user biased gradient aggregation, and determining a corresponding over-the-air computation communication model; (4) processing a signal by a receiver using an incoherent energy detection method without cooperation between the receiver and a transmitter; and (5) determining a federated learning security mechanism method based on resistance against parameter biased aggregation, and completing an updating training process of the federated learning system model.

Abstract: The present disclosure relates to the field of EV-DWPT (electric vehicle dynamic wireless power transfer), and specifically discloses a double solenoid EV-DWPT system and a parameter optimization method thereof. The system is provided with a magnetic coupling mechanism, comprising a transmitting structure and a receiving structure. The transmitting structure includes a plurality of double solenoid transmitting rails arranged equidistantly along a road direction. Each double solenoid transmitting rail includes a square tubular magnetic core perpendicular to the road surface, and transmitting solenoids wound spirally using one and the same Litz wire wound in opposite directions.

Abstract: A method of manufacturing a semiconductor structure includes: providing a base and a dielectric layer on the base, the base in an array region being provided with discrete capacitive contact plugs and a first conductive layer being formed on a top surface of the capacitive contact plugs; sequentially forming a conversion layer and a target layer on the first conductive layer and the dielectric layer, the target layer in the array region and the first circuit region being provided with first openings through the target layer; patterning the target layer in the array region as well as in the first circuit region and the second circuit region to form a second opening and a third opening; etching the conversion layer to form a first trench; forming a filling layer filling the first trench and removing the conversion layer to form a second trench filled by a second conductive layer.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate, and forming a stacked structure on the substrate; forming a hard mask layer on the stacked structure, where the hard mask layer includes a first etched window, and the first etched window exposes part of a top surface of the stacked structure; forming a photoresist layer, where the photoresist layer covers the first etched window; and trimming the photoresist layer for a plurality of times, after each trimming of the photoresist layer, etching the stacked structure according to a trimmed photoresist layer, and forming a plurality of steps in the stacked structure along a direction away from the substrate.

Abstract: Provided is a curved liquid crystal display panel, including a color film substrate and an array substrate. An orthographic projection of the color film substrate on the array substrate is within the array substrate. The color film substrate includes a first side surface and a second side surface. The array substrate includes a third side surface and a fourth side surface. The first side surface is adjacent to and staggered from the third side surface. The second side surface is adjacent to and staggered from the fourth side surface. At positions where the third side surface and the fourth side surface are disposed, each of a side, proximal to the color film substrate, of the array substrate and a side, distal from the color film substrate, of the array substrate includes a structure formed by a grinding process.

Abstract: Disclosed are a double-sided solar cell and a preparation method therefor. The double-sided solar cell comprises: a silicon wafer having a PN junction, and a front first silicon oxide layer, a front second silicon oxide layer, a front first nitrogen-containing silicon compound layer, a front second nitrogen-containing silicon compound layer, and a front third silicon oxide layer that are located on one side of an N-type layer of the silicon wafer and are sequentially stacked along a direction away from the silicon wafer; and a passivation layer, a back silicon oxide layer, a back first nitrogen-containing silicon compound layer, and a back second nitrogen-containing silicon compound layer that are located on one side of a P-type layer of the silicon wafer and are sequentially stacked along the direction away from the silicon wafer.

Abstract: A semiconductor structure includes a base provided with a conductive contact hole, a metal sulfide layer formed in the conductive contact hole and covering a bottom wall of the conductive contact hole, a semi-metal layer formed on a surface of the metal sulfide layer, a barrier layer covering a surface of the semi-metal layer and a sidewall of the conductive contact hole and a conductive contact structure disposed in an accommodation hole delimited by the barrier layer.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, the substrate having a first surface and a second surface opposite to each other, and a transistor being arranged on the second surface; forming release holes in the substrate, the release holes extending into the transistors, bottoms of the release holes being located in channel regions of the transistors, and top surfaces of the release holes being flush with the first surface; and forming a conductive structure in the release holes.

Abstract: Embodiments of the disclosure relate to the semiconductor field, and provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate that has a bit line extending in a first direction; an active pillar located on the bit line, in which a bottom surface of the active pillar is in contact with the bit line, and the active pillar is doped with an N-type element; an inversion region located on the side surface of the active pillar, and doped with a P-type element; a dielectric layer and a word line extending in a second direction, in which the dielectric layer and the word line wrap part of the inversion region, and the dielectric layer is located between the word line and the inversion region.

Abstract: Embodiments of the present disclosure provide a manufacturing method of a semiconductor device and a semiconductor device, relating to the technical field of semiconductors. The manufacturing method of a semiconductor device includes: providing a first substrate; forming an array structure layer on the first substrate; forming an insulating material layer on the array structure layer; forming a second substrate on the insulating material layer; and forming a transistor of a peripheral circuit layer on the second substrate.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing an initial structure, where the initial structure includes a base and an initial trench, and the initial trench exposes part of active area structures; forming a capacitor contact structure, where the capacitor contact structure covers the exposed part of the active area structures, and the capacitor contact structure includes a first groove; forming a metal-semiconductor contact structure, where the metal-semiconductor contact structure at least covers a top surface of the capacitor contact structure and fills the first groove; forming a barrier structure, where the barrier structure covers the metal-semiconductor contact structure and an exposed sidewall of the initial trench; and forming a conductive structure, where the conductive structure is connected to the capacitor contact structure through the metal-semiconductor contact structure.

Abstract: Embodiments disclose a capacitor array structure and a method for fabricating a capacitor array structure. The method includes: after forming a first capacitor hole, providing a bonded wafer including a second substrate, a second supporting layer and a second sacrificial layer stacked in sequence, and bonding the bonded wafer to a stacked structure, wherein a surface of the second sacrificial layer away from the second supporting layer is a bonding surface; forming a second capacitor hole, the second capacitor hole penetrating into the bonded wafer at least along a thickness direction to expose the first capacitor hole, such that the first capacitor hole is connected with the second capacitor hole.

Abstract: A method for manufacturing a semiconductor device includes following operations. A substrate is provided, including memory array region. A plurality of bit lines are formed in memory array region. First insulating material is filled between the plurality of bit lines. A plurality of trenches intersecting with bit lines are provided in first insulating material. Memory array region includes inner region and boundary region outside same. Second insulating material is filled in trenches to form spacing lines. Second insulating material is also deposited above bit lines, spacing lines and first insulating material to form cap material layer. Etching process is performed to form node contact holes, including following operations. Cap material layer is etched to form cap layer covering bit lines, spacing lines and first insulating material in boundary region. First insulating material in inner region is removed by etching with cap layer as mask to from node contact holes.

Abstract: Embodiments provide method for fabricating a semiconductor structure, and a semiconductor structure. The method includes: providing a substrate, a thin-film stack structure being formed on the substrate; forming a first groove and a second groove in the thin-film stack structure, and forming write transistors in the first groove, the second groove extending along a first direction, and the second groove being positioned between adjacent two of the write transistors in a second direction; removing a part of the thin-film stack structure by etching using the second groove to form a first hole and a second hole respectively, forming a write word line in the first hole, and forming a write bit line in the second hole; forming a first via on an upper surface of the thin-film stack structure, and forming a storage node in the first via; and forming a read transistor, a read bit line and a lead.

Abstract: This invention relates to a semiconductor structure and a fabrication method therefor. The method for fabricating a semiconductor structure includes: providing a substrate, where a shallow trench isolation structure is formed on the substrate; forming a plurality of transistor accommodating grooves in the active regions, where there is a spacing between the transistor accommodating groove and the shallow trench isolation structure; forming a columnar structure in the transistor accommodating groove, where the columnar structure includes a source, a conductive channel, and a drain that are sequentially disposed in a direction away from the substrate; etching the active region located within the spacing and the active region located between adjacent columnar structures in the same active region to form a bit line trench, where the bit line trench surrounds the source; and forming a bit line that surrounds and connects the source in the bit line trench.

Abstract: Disclosed are a wireless signal performance adjustment apparatus and method, and a wireless communication terminal. The wireless signal performance adjustment apparatus comprises a monitoring unit, a control unit, a measurement unit and an adjustment unit.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: depositing a thin-film stacked structure on a substrate; forming a first hole in the thin-film stacked structure; growing an epitaxial silicon pillar in the first hole; etching the thin-film stacked structure and the epitaxial silicon pillar along a first direction to form a first trench, the first trench passing through a center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half pillar and a second half pillar; forming a first isolation layer; forming a first channel region of a first doping type, and forming a second channel region of a second doping type; and forming a gate dielectric layer and a gate conductive layer on a surface of each of the first channel region and the second channel region.