Abstract: According to embodiments of the present invention, the gate lines of the array substrate receive the gate scanning signal in a preset time period. Specifically, the gate lines of pixel units in odd rows are receiving the gate scanning signal in the first time interval of the preset time period, and the gate lines of pixel units in even rows are receiving the gate scanning signal in the second time interval of the preset time period.

Abstract: The present disclosure relates to a driving device and a driving method of a liquid crystal display device and a liquid crystal display device. The liquid crystal display device comprises a display panel. The driving method comprising following steps of: displaying a current image by driving the display panel in a current reverse driving mode; detecting a variation value of a common voltage of the display panel during a prescribed period of time, and determining whether the variation value of the common voltage is greater than a prescribed threshold voltage variation; and in case that the variation value of the common voltage is greater than the prescribed threshold voltage variation, determining an occurrence of an image flickering and changing the current reverse driving mode. According to the present disclosure, the flickering of the liquid crystal display device can be reduced.

Abstract: A 3D display method and a 3D display device are provided. The 3D display method comprises: decomposing one frame of picture into a left-eye picture and a right-eye picture, the left-eye picture including pixel information of a left-eye perspective picture, and the right-eye picture including pixel information of a right-eye perspective picture; decomposing the left-eye picture into continuously displayed left-eye sub-pictures, and decomposing the right-eye picture into continuously displayed right-eye sub-pictures. By decomposing one frame of picture into the left-eye sub-pictures and right-eye sub-pictures continuously displayed, each frame of the sub-picture can only display partial picture information, which reduces or eliminates the 3D crosstalk problem when the left-eye perspective picture and the right-eye perspective picture alternate, and improves the 3D display effect.

Abstract: Compared with the prior art, in the processing method provided by the present disclosure, a corresponding monocular frame mixed image signal that includes a part of successive monocular frame image signals and a part of successive black picture image signals is inserted after the monocular frame image signal. Therefore at the time of 3D image display, since the monocular frame mixed image signal includes part of the monocular frame image signals and part of the black picture image signals, the 3D image crosstalk phenomenon can be efficiently improved. Moreover, since the monocular frame mixed image signal only has part of the black picture image signals, a better brightness evenness can be obtained in display by reducing the proportion of the black picture image signals in the monocular frame mixed image signal.

Abstract: The present invention provides an array substrate, a 3D display device and a driving method for the same, and belongs to the field of 3D display. Wherein, the array substrate comprises: a substrate, and 2n rows of pixel units being arranged on the substrate in a matrix form, the array substrate further comprises gate lines corresponding to the pixel units in each row, and each of the gate lines is connected to the gate electrodes of thin film transistors in corresponding pixel units, wherein the gate line corresponding to pixel units in the (2k?1)th row of pixel units or the gate line corresponding to the 2kth row receives the gate scanning signal in a predetermined time period, wherein k is a natural number which is not less than 1 and not greater than n.

Abstract: The present invention belongs to the field of 3D display, and provides an array substrate, a 3D display device and a driving method for the same. The array substrate comprising a substrate and m rows and 2n columns of pixel units formed on the substrate in a matrix form. The array substrate further comprises data lines each of which corresponds to the pixel units in each row and gate lines each of which corresponds to the pixel units in each column. Each of the data lines is connected to source electrodes of thin film transistors in the corresponding pixel units, and each of gate lines is connected to gate electrodes of the thin film transistors in the corresponding pixel units. The gate lines receive a gate scanning signal according to a predetermined period.

Abstract: According to embodiments of the present invention, the gate lines of the array substrate receive the gate scanning signal in a preset time period. Specifically, the gate lines of pixel units in odd rows are receiving the gate scanning signal in the first time interval of the preset time period, and the gate lines of pixel units in even rows are receiving the gate scanning signal in the second time interval of the preset time period.

Abstract: A driving circuit for a LCD backlight source comprising a BOOST structure which comprises a capacitor C12, a capacitor C13, an inductor L2, a diode D2, and a MOSFET, wherein the driving circuit further comprises a capacitor C11, a capacitor C14, a diode D3, and a diode D4. One terminal of the diode D3 is connected to one terminal of the capacitor C13, and the other terminal is connected to one terminal of the diode D4; the other terminal of the diode D4 is connected to one terminal of the capacitor C14 which is the output terminal of the circuit, and the other terminal of the capacitor C14 is grounded; one terminal of the capacitor C11 is connected between the inductor L2 and the diode D2, and the other terminal of the capacitor C11 is connected between the diode D3 and the diode D4.

Abstract: A driving circuit for a LCD backlight source comprising a BOOST structure which comprises a capacitor C12, a capacitor C13, an inductor L2, a diode D2, and a MOSFET, wherein the driving circuit further comprises a capacitor C11, a capacitor C14, a diode D3, and a diode D4. One terminal of the diode D3 is connected to one terminal of the capacitor C13, and the other terminal is connected to one terminal of the diode D4; the other terminal of the diode D4 is connected to one terminal of the capacitor C14 which is the output terminal of the circuit, and the other terminal of the capacitor C14 is grounded; one terminal of the capacitor C11 is connected between the inductor L2 and the diode D2, and the other terminal of the capacitor C11 is connected between the diode D3 and the diode D4.