Abstract: Photonic data routing in optical networks is expected overcome the limitations of electronic routers with respect to data rate, latency, and energy consumption. However photonics-based routers suffer from dynamic power consumption, and non-simultaneous usage of multiple wavelength channels when microrings are deployed and are sizable in footprint. Here we show a design for the first hybrid photonic-plasmonic, non-blocking, broadband 5×5 router based on 3-waveguide silicon photonic-plasmonic 2×2 switches. The compactness of the router (footprint <200 ?m2) results in a short optical propagation delay (0.4 ps) enabling high data capacity up to 2 Tbps. The router has an average energy consumption ranging from 0.1˜1.0 fJ/bit depending on either DWDM or CDWM operation, enabled by the low electrical capacitance of the switch. The total average routing insertion loss of 2.

Abstract: A request is received from a client for determining task completion of a first set of tasks associated with attributes, the first set of tasks scheduled to be performed within a first time period. For each of the attributes, a completion rate of one or more of a second set of tasks is calculated that are associated with the attribute. The second set of tasks has been performed during a second time period in the past. An isotonic regression operation and/or temporal smoothing are performed on the completion rates associated with the attributes of the second set of tasks that have been performed during the second time period to calibrate the completion rates. Possible completion for the attributes of the first set of tasks to be performed in the first time period is calculated based on the calibrated completion rates of the second set of tasks.

Abstract: A first request is received at a server for a view of a chart graph from a client device over a network. The first request includes a first view identifier (ID) identifying a first of the views and a first filtering parameter for filtering data to be associated with the first view. A second request is transmitted to a CRM system over a network to retrieve live data associated with one or more chart elements of the first view. The second request includes information identifying the first filtering parameter such that only live data satisfying the first filtering parameter is retrieved from the CRM system. In response to the live data received from the remote CRM system, the live data is transmitted to the client device, wherein the client device renders a chart graph based on the live data and displays the chart graph at the client device.

Abstract: The Hybrid Photonic Plasmonic Interconnect (HyPPI) combines both low loss photonic signal propagation and passive routing with ultra-compact plasmonic devices. These optical interconnects therefore uniquely combine fast operational data-bandwidths (in hundreds of Gbps) for light manipulation with low optical attenuation losses by hybridizing low loss photonics with strong light-matter-interaction plasmonics to create, modulate, switch and detect light efficiently at the same time. Initial implementations were considered for on-chip photonic integration, but also promising for free space or fiber-based systems. In general two technical options exist, which distinguished by the method the electric-optic conversion is executed: the extrinsic modulation method consists of an continuous wave source such as an LED or laser operating at steady power output, and signal encoding is done via an electro-optic modulator downstream of the source in the interconnect.

Abstract: An optical-electronic device can be controlled by a bias voltage to simulate an electronic component such as a resistor, capacitor, inductor with resistor, or capacitor with resistor. The optical-electronic device can be connected in a network to perform computations, model problems, simulate properties such as physical properties (for instance heat transfer), and achieve circuit performances to carry out computations in the analog domain, all at faster speed with smaller size and at less energy.

Abstract: Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching.

Abstract: Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.

Abstract: The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.

Abstract: The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

Abstract: Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.

Abstract: Disclosed herein is a method for fabricating an ultra-fine nanowire by combining a trimming process and a mask blocking oxidation process. The ultra-thin nanowire is fabricated by a combination of performing a trimming process on a mask to reduce a width of the mask and blocking an oxidation through the mask. A diameter of the floated ultra-thin nanowire fabricated by the method is controlled to 20 nm below by a thickness of a deposited silicon oxide film, a width of the silicon oxide nanowire after trimming, and a time and a temperature for performing a wet oxidation process. Also, since a speed of the wet oxidation process is faster, the width of the nanowire obtained by a conventional photolithography is reduced faster. Moreover, when fabricating an ultra-thin nanowire by using the method, the cost is reduced and it is more feasible to be implemented.

Abstract: Disclosed herein is a method for fabricating an ultra fine nanowire, which relates to a manufacturing technology of a microelectronic semiconductor transistor. This method obtains a suspended ultra fine nanowire base on a combination of a mask blocking oxidation process and a stepwise oxidation process. A diameter of the suspended ultra fine nanowire fabricated by this method is precisely controlled to 20 nm by controlling a thickness of a deposited silicon nitride film and a time and temperature of the two oxidation process. Since a speed of a dry oxidation process is slower, the size of the final nanowire may be precisely controlled. This method can be used to fabricate an ultra fine nanowire with a lower cost and a higher applicability.

Abstract: The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

Abstract: Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching.

Abstract: The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.