Abstract: A system and method are presented for saving and restoring the state of a diagnostic module in a microprocessor. The diagnostic module contains a complex break state machine, capable of halting the microprocessor at specified breakpoints. These breakpoints are based on combinations of instruction locations and/or data values, along with previous machine states. A problem occurs with prior art diagnostic modules when the processor returns from an exception occurring during a fix-up cycle inserted to handle a data load miss associated with an instruction located in a branch delay slot (the location immediately following a conditional branch instruction). Under these circumstances, the exception handler restores the program counter to the location of the branch instruction, causing the branch to be re-executed. The prior art state machine erroneously updates its internal state a second time when the branch is re-executed.

Abstract: Methods and structure for improving accuracy of a master delay line associated with slave delay lines wherein the master delay line is design utilizing a higher clock frequency then the clock frequency applied to associated slave delay lines. The higher clock frequency applied to the master delay line in accordance with the present invention permits the master delay line to be comprised of fewer delay elements than would be the case for a master delay line using the same basic clock frequency as associated slave delay lines. The lower number of delay elements comprising the master delay line (i.e., the shorter length of the master delay line) helps reduce static phase errors associated with the master delay line inherent in the design, layout and fabrication of a longer delay line.

Abstract: A memory controller includes an input command decoder circuit for generating an input command, a state machine controller coupled to receive the input command from the input command decoder circuit and generate a state machine input instruction therefrom, a state machine array comprised of a plurality of state machines coupled to receive the input command and state machine input instructions from the state machine controller and to generate state machine output instructions therefrom, and an output command decoder circuit for receiving a state machine output command and generating an output command therefrom for transmission to a memory, associated with the memory controller, comprised of a plurality of memory banks. A first state machine execute a state machine input instruction transmitted, with the input conunand, to all state machines if a memory address contained within the input command corresponds to an address for a corresponding memory bank.

Abstract: An apparatus and method for translating variable-length instructions to fixed-length instructions. The apparatus includes instruction decompression logic and caching logic. The instruction decompression logic receives a first portion of an instruction data block, an output signal produced by the caching logic, and a control signal during a time period. The instruction decompression logic produces a fixed-length instruction during the time period dependent upon the first portion of the instruction data block, the output signal produced by the caching logic, and the control signal. The caching logic includes a storage unit. During the time period, the caching logic receives a second portion of the instruction data block and the control signal. The caching logic stores the second portion of the instruction data block within the storage unit during the time period dependent upon the control signal.

Abstract: A computer system incorporates bus snooping with a bus that does not enable bus snooping, such as the Advanced High-Performance Bus (AHB), to maintain cache coherency between caching devices and shared memory. Bus snooping capabilities are enabled by a stand-alone bus snooping device connected to the bus and the caching device or by bus snooping functions incorporated into the caching device. The bus snooping device monitors communications on the bus and causes invalidation of cached information to maintain cache coherency before the communications complete.

Abstract: Methods and structure in a memory controller for sequencing memory device page activation commands to improve memory bandwidth utilization. In a synchronous memory device such as SDRAM or DDR SDRAM, an “activate” command precedes a corresponding “read” or “write” command to ensure that the page or row to be accessed by the “read” or “write” is available (“open”) for access. Latency periods between the activation of the page and the readiness ofthe page for the corresponding read or write command are heretofore filled withnop commands. The present invention looks ahead for subsequent read and write commands and inserts activation commands (hidden activates) in nop command periods of the SDRAM device to prepare a page in another bank for a read or write operation to follow. This sequencing of activate commands overlaps the required latency with current read or write burst operations.

Abstract: A programmable delay feature useful to reduce contention related delays between a memory controller device and a plurality of master devices sharing access to a memory subsystem through the single memory controller device. The programmable delay line is programmed to an optimal delay value for each master device prior to returning data to the requesting master device. A configuration register associated with the memory controller stores the optimal value for the delay line for the present application of the controller. Firmware operable on a processor coupled to the memory controller (or other programmable master device) may determine the optimal delay line value for the system. The optimal delay line value so determined is then stored in the memory controller's configuration register.

Abstract: A memory controller includes a pair of input command decoders and a pair of multiplexers. If the memory controller receives a data transfer request related to a read or write burst which will stay within a page of memory, the first input command decoder circuit generates a first input command which is then passed, in sequence, by the first and second multiplexers. Conversely, if the data transfer request relates to a read or write burst which will burst over a page of the memory, the second input command decoder circuit generates second and third input commands. The second input command passes through the second multiplexer circuit while the third input command is held in a command register. The third input command is subsequently passed through the first and second multiplexers.

Abstract: A method and apparatus are provided for addressing a memory device. The apparatus receives a system address from a memory access device having an endianess. The system address has a word address bit corresponding to word boundaries within the memory device. The apparatus selectively inverts the word address bit as a function of the endianess of the memory access device to produce a selectively modified system address. The apparatus then accesses a memory location with the memory device based on the selectively modified system address.