Patents by Inventor Shuangdi ZHAO

Shuangdi ZHAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11475926
    Abstract: The present disclosure relates to integrated circuits, and more particularly, to a sense amplifier circuit for current sensing in a memory structure and methods of manufacture and operation. In particular, the present disclosure relates to a circuit including: a sensing circuit including a first set of transistors, at least one data cell circuit, and a reference cell circuit; a reference voltage holding circuit comprising a second set of transistors and a bitline capacitor; and a comparator differential circuit which receives a data sensing voltage signal from the sensing circuit and a reference voltage level from the reference voltage holding circuit and outputs an output signal.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: October 18, 2022
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Xiaoxiao Li, Xiaoli Hu, Shuangdi Zhao, Xi Cao, Wei Zhao, Xueqiang Dai
  • Patent number: 10978143
    Abstract: A structure includes a multi-port memory including a multiple transistor bitcell single ended read port and a write port, a read circuit which is connected to a multiple transistor bitcell circuit and is also configured to evaluate the multiple transistor bitcell single ended read port, and a timer circuit for the single ended read port and which is configured to generate two successive read pulses in one clock cycle for the multi-port memory.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 13, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: George M. Braceras, Xiaoli Hu, Wei Zhao, Igor Arsovski, Yuzheng Jin, Hao Pu, Shuangdi Zhao, Qing Li
  • Publication number: 20210065784
    Abstract: A structure includes a multi-port memory including a multiple transistor bitcell single ended read port and a write port, a read circuit which is connected to a multiple transistor bitcell circuit and is also configured to evaluate the multiple transistor bitcell single ended read port, and a timer circuit for the single ended read port and which is configured to generate two successive read pulses in one clock cycle for the multi-port memory.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 4, 2021
    Inventors: George M. BRACERAS, Xiaoli HU, Wei ZHAO, Igor ARSOVSKI, Yuzheng JIN, Hao PU, Shuangdi ZHAO, Qing LI