Patents by Inventor Shuangshuang Pu
Shuangshuang Pu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11933724Abstract: Disclosed are a device of complex gas mixture detection based on optical-path-adjustable spectrum detection and a method therefor, and the device includes: a light source configured for generating an incident beam and emitting the incident beam into an optical gas cell; the optical gas cell, including a cavity configured for accommodating a gas sample, and a reflection module group configured for reflecting the incident beam and a track arranged in the cavity, where the track is consistent with a light path of the light beam in the cavity; a detector module that is connected with the track in a relatively movable manner and is configured for receiving light beams and obtaining spectral data, where an optical path is changed by moving the detector module relative to the track; and a data acquisition unit that is configured for acquiring the spectral data obtained by the detector module.Type: GrantFiled: December 1, 2023Date of Patent: March 19, 2024Assignee: Hubei University of TechnologyInventors: Yin Zhang, Xiaoxing Zhang, Ran Zhuo, Zhiming Huang, Guozhi Zhang, Dibo Wang, Shuangshuang Tian, Mingli Fu, Yunjian Wu, Yan Luo, Shuo Jin, Jinyu Pu, Yalong Li
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Patent number: 8901644Abstract: Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.Type: GrantFiled: September 9, 2011Date of Patent: December 2, 2014Assignee: Peking UniversityInventors: Ru Huang, Yujie Ai, Zhihua Hao, Shuangshuang Pu, Jiewen Fan, Shuai Sun, Runsheng Wang, Xiaoyan Xu
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Patent number: 8722312Abstract: The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.Type: GrantFiled: September 9, 2011Date of Patent: May 13, 2014Assignee: Peking UniversityInventors: Ru Huang, Yujie Al, Zhihua Hao, Shuangshuang Pu, Jiewen Fan, Shuai Sun, Runsheng Wang, Xia An
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Publication number: 20130168759Abstract: Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.Type: ApplicationFiled: September 9, 2011Publication date: July 4, 2013Applicant: PEKING UNIVERSITYInventors: Ru Huang, Yujie Ai, Zhihua Hao, Shuangshuang Pu, Jiewen Fan, Shuai Sun, Runsheng Wang, Xiaoyan Xu
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Patent number: 8288238Abstract: The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching.Type: GrantFiled: September 25, 2010Date of Patent: October 16, 2012Assignee: Peking UniversityInventors: Ru Huang, Yujie Ai, Zhihua Hao, Chunhui Fan, Shuangshuang Pu, Runsheng Wang, Quanxin Yun
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Publication number: 20120238097Abstract: Disclosed herein is a method for fabricating a fine line, which belongs to a field of ultra-large-scale integrated circuit manufacturing technology. In the invention, three trimming mask processes are performed to effectively improve a profile of the line and greatly reduce the LER (line edge roughness) of the line. At the same time, the invention is combined with a sidewall process, so that a nano-scaled fine line can be successfully fabricated and precisely controlled to 20 nm. Thus, a nano-scaled line with an optimized LER can be fabricated over the substrate.Type: ApplicationFiled: September 29, 2011Publication date: September 20, 2012Inventors: Ru Huang, Shuangshuang Pu, Yujie Ai, Zhihua Hao, Runsheng Wang
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Publication number: 20120190202Abstract: The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.Type: ApplicationFiled: September 9, 2011Publication date: July 26, 2012Applicant: PEKING UNIVERSITYInventors: Ru Huang, Yujie Al, Zhihua Hao, Shuangshuang Pu, Jiewen Fan, Shuai Sun, Runsheng Wang, Xia An
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Publication number: 20120115297Abstract: The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching.Type: ApplicationFiled: September 25, 2010Publication date: May 10, 2012Applicant: PEKING UNIVERSITYInventors: Ru Huang, Yujie Ai, Zhihua Hao, Chunhui Fan, Shuangshuang Pu, Runsheng Wang, Quanxin Yun