Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The method for manufacturing the semiconductor structure includes: providing a substrate, in which the substrate includes an array area and a peripheral area adjacent to each other, and the array area includes a buffer area connected to the peripheral area; forming a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a third dielectric layer, which are successively stacked onto one another, on the substrate, forming a groove-type lower electrode, which at least penetrates through the third dielectric layer and the second supporting layer, in the buffer area; removing the third dielectric layer through a wet etching process; and etching the second supporting layer in the peripheral area after removing the third dielectric layer.

Abstract: A three-dimensional (3D) memory device includes a stack structure including interleaved first conductive layers and first dielectric layers, and a channel structure extending through the stack structure along a first direction in contact with a first semiconductor layer at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The semiconductor channel includes an angled structure, and a first width of the semiconductor channel at the bottom portion of the channel structure below the angled structure is smaller than a second width of the semiconductor channel at an upper portion of the channel structure above the angled structure.

Abstract: Disclosed are a device of complex gas mixture detection based on optical-path-adjustable spectrum detection and a method therefor, and the device includes: a light source configured for generating an incident beam and emitting the incident beam into an optical gas cell; the optical gas cell, including a cavity configured for accommodating a gas sample, and a reflection module group configured for reflecting the incident beam and a track arranged in the cavity, where the track is consistent with a light path of the light beam in the cavity; a detector module that is connected with the track in a relatively movable manner and is configured for receiving light beams and obtaining spectral data, where an optical path is changed by moving the detector module relative to the track; and a data acquisition unit that is configured for acquiring the spectral data obtained by the detector module.

Abstract: In certain aspects, a first opening extending vertically through a first dielectric deck including a first plurality of interleaved sacrificial layers and dielectric layers above a substrate is formed. A high-k dielectric layer and a channel sacrificial layer free of polysilicon are subsequently formed along a sidewall of the first opening. A second opening extending vertically through a second dielectric deck including a second plurality of interleaved sacrificial layers and dielectric layers on the first dielectric deck is formed to expose the channel sacrificial layer in the first opening. The channel sacrificial layer is removed in the first opening. A memory film and a semiconductor channel are subsequently formed over the high-k dielectric layer along sidewalls of the first and second openings.

Abstract: Provided are a content search method, apparatus, and device, and a storage medium. The present disclosure enables: receiving a search content; and displaying a plurality of answer viewpoints and first contents in a search result interface, wherein each answer viewpoint corresponds to one category of search results, the search results are results obtained by searching the search content, the first contents comprises keywords, the keywords are used for indicating reasons for displaying a target answer viewpoint among the plurality of answer viewpoints, and the keywords are extracted from a target category of search results corresponding to the target answer viewpoint.

Abstract: The application provides a data sending method and a communication apparatus to avoid signaling overheads caused by scheduling by a network device, and a terminal device can flexibly select a quantity of repeated transmissions based on an actual situation, so that data transmission performance is improved. The network device sends configuration information of a receive power to the terminal device. After receiving the configuration information of the receive power, the terminal device determines a quantity of repeated transmissions of target data based on the configuration information of the receive power. After determining the quantity of repeated transmissions of the target data, the terminal device sends the target data to the network device based on the quantity of repeated transmissions of the target data.

Abstract: A memory device includes a stack structure, channel structures, and a slit structure. The stack structure includes interleaved conductive layers and dielectric layers, and the conductive layers include a plurality of word lines. Each of the channel structures extends vertically through the stack structure. The slit structure extends vertically through the stack structure. An outer region of the stack structure includes a staircase structure, and the interleaved conductive layers and dielectric layers in a bottom portion of the stack structure are wider than the interleaved conductive layers and dielectric layers in a top portion of the stack structure. A first outer width of the slit structure in the bottom portion of the stack structure is greater than a second outer width of the slit structure in the top portion of the stack structure.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, in which the substrate includes an array region and a peripheral region adjacent to each other, and the array region includes a buffer region connected with the peripheral region; a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a third dielectric layer, which are successively stacked onto one another, are formed on the substrate; a groove-type lower electrode, which at least penetrates through the third dielectric layer and the second supporting layer, is formed in the buffer region; the third dielectric layer is removed through a wet etching process; and the second supporting layer in the peripheral region is etched after the third dielectric layer is removed.

Abstract: A data processing method and data processing apparatus are provided. The data processing method includes: acquiring multiple input tensors as input parameters for calculation process; for each input tensor, using M input sub-tensors that are combined to represent the input tensor; for each of the input tensors, replacing the input tensors with the M input sub-tensors that are combined to represent the input tensor, and performing the calculation process to obtain a calculation result. The data processing method increases the applicable scenarios of calculation process, effectively utilizes the powerful calculation ability of the originally provided low-accuracy floating points, and greatly improves the overall calculation efficiency.

Abstract: A method for forming a capacitor includes: providing a substrate with an electric contact portion; forming a supporting layer and a sacrificial layer which are alternately laminated on a surface of the substrate, wherein the topmost layer is a supporting layer; forming a capacitor hole penetrating through the supporting layer and the sacrificial layer and exposing the electric contact portion; forming a bottom electrode layer covering an inner surface of the capacitor hole; forming a protective layer covering a surface of the bottom electrode layer; removing the sacrificial layer, during which the bottom electrode layer being protected by the protective layer; removing the protective layer; and sequentially forming a capacitor dielectric layer and a top electrode layer.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. The 3D memory device includes a doped semiconductor layer, a source select gate line disposed on the doped semiconductor layer, a stack structure including interleaved conductive layers and dielectric layers formed on the source select gate line, and a channel structure extending through the stack structure and the source select gate line and in contact with the doped semiconductor layer. The channel structure includes a semiconductor channel and a memory film. The source select gate line is in contact with the semiconductor channel.

Abstract: A three-dimensional (3D) memory device includes a stack structure including interleaved first conductive layers and first dielectric layers, a channel structure extending through the stack structure along a first direction in contact with a first semiconductor layer at a bottom portion of the channel structure, and a slit structure extending through the stack structure along the first direction. The slit structure includes a slit core, and a second dielectric layer surrounding the slit core. A first width of the second dielectric layer near the first semiconductor layer is larger than a second width of the second dielectric layer away from the first semiconductor layer.

Abstract: A semiconductor structure includes: a through silicon via penetrating a base; and a protection structure, including: a conductive first test ring and a conductive second test ring both arranged around the through silicon via and electrically insulated from the through silicon via; a first dielectric layer located between the first test ring and the second test ring and configured to electrically isolate the first test ring from the second test ring; and a first connection layer located in the first dielectric layer and configured to be electrically connected to the first test ring and the second test ring.

Abstract: A semiconductor structure includes: a base, including a substrate, a first isolation layer, a first dielectric layer, and a stop layer that are formed in a stack manner, a first contact hole being formed in the base; a first insulating layer and a first barrier layer sequentially formed on an inner wall of the first contact hole, a first contact structure being disposed in the first contact hole; a protective layer covering an upper surface of the first contact structure; a second dielectric layer and a second isolation layer sequentially stacked on the protective layer, a second contact hole being formed in the base; and a second barrier layer formed on an inner wall of the second contact hole and a second contact structure disposed in the second contact hole.

Abstract: A semiconductor structure includes: a base; a first conductive layer, having a portion located within the base and a remaining portion protruding above the base; a barrier layer on the base and at least on a sidewall of the first conductive layer protruding from the base; a dielectric layer on the barrier layer; and a second conductive layer penetrating the dielectric layer and the barrier layer, in contact with the sidewall of the barrier layer, and in contact with at least a portion of the upper surface of the first conductive layer.

Abstract: The present application provides a semiconductor structure fabrication method, a semiconductor structure and a memory. The semiconductor structure fabrication method includes: providing a substrate, the substrate including a first surface and a second surface opposite to each other; forming a first dielectric layer on the first surface of the substrate, wherein semiconductor devices are formed in the first dielectric layer; forming first trenches extending into the substrate in the first dielectric layer; forming a first barrier layer on the first dielectric layer, the first barrier layer covering inner walls of the first trenches and a surface of the first dielectric layer; forming second trenches corresponding to the first trenches on the second surface of the substrate; and forming a second barrier layer on the substrate, the second barrier layer covering the second surface and inner walls of the second trenches.

Abstract: A method for manufacturing a semiconductor structure, including: providing a base; forming a Through Silicon Via (TSV) in the base, with a depth of the TSV being less than a thickness of the base; and forming a liner layer on a sidewall and the bottom of the TSV, and forming a conductive layer in the TSV, the liner layer including a polish-stop layer.

Abstract: The present disclosure relates to a manufacturing method of a semiconductor structure, including: the base includes an array region and a peripheral region a depth of the TSV is smaller than a thickness of the base; forming a filling dielectric layer; forming a conductive layer in the TSV, the conductive layer is flush with an upper surface of the filling dielectric layer; forming first metal layers an upper surface of each of the first metal layers is flush with an upper surface of the conductive layer; forming a first dielectric layer; and forming a first interconnection structure and second interconnection structures at the same time in the first dielectric layer, a bottom of the first interconnection structure is in contact with one of the first metal layers, and bottoms of the second interconnection structures are in contact with the conductive layer.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, in which the substrate includes an array region and a peripheral region adjacent to each other, and the array region includes a buffer region connected with the peripheral region; a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a third dielectric layer, which are successively stacked onto one another, are formed on the substrate; a groove-type lower electrode, which at least penetrates through the third dielectric layer and the second supporting layer, is formed in the buffer region; the third dielectric layer is removed through a wet etching process; and the second supporting layer in the peripheral region is etched after the third dielectric layer is removed.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The method for manufacturing the semiconductor structure includes: providing a substrate, in which the substrate includes an array area and a peripheral area adjacent to each other, and the array area includes a buffer area connected to the peripheral area; forming a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a third dielectric layer, which are successively stacked onto one another, on the substrate,; forming a groove-type lower electrode, which at least penetrates through the third dielectric layer and the second supporting layer, in the buffer area; removing the third dielectric layer through a wet etching process; and etching the second supporting layer in the peripheral area after removing the third dielectric layer.