Patents by Inventor Shuang Wu Huang

Shuang Wu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Castellation wafer level packaging of integrated circuit chips
    Patent number: 7304375
    Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: December 4, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Suan Jeung Boon, Yong Poo Chia, Siu Waf Low, Meow Koon Eng, Swee Kwang Chua, Shuang Wu Huang, Yong Loo Neo, Wei Zhou
  • Castellation wafer level packaging of integrated circuit chips
    Patent number: 7271027
    Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: September 18, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Suan Jeung Boon, Yong Poo Chia, Siu Waf Low, Meow Koon Eng, Swee Kang Chua, Shuang Wu Huang, Yong Loo Neo, Wei Zhou
  • Castellation wafer level packaging of integrated circuit chips
    Patent number: 7193312
    Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: March 20, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Suan Jeung Boon, Yong Poo Chia, Siu Waf Low, Meow Koon Eng, Swee Kwang Chua, Shuang Wu Huang, Yong Loo Neo, Wei Zhou