Abstract: The present disclosure provides a method for estimating a frequency offset, including: extracting sampling points from an input signal according to preset intervals to obtain a plurality of groups of sampling points, with the preset intervals of the groups of sampling points being different; performing processes on a current sampling point and the groups of sampling points to obtain data of arguments of complex numbers corresponding to the preset intervals; and determining an estimation value of a frequency offset of a current input signal according to the data of arguments of complex numbers corresponding to the preset intervals. The present disclosure further provides an apparatus for estimating a frequency offset, an electronic device and a computer-readable medium.

Abstract: The present disclosure provides a method for estimating a frequency offset, including: extracting sampling points from an input signal according to preset intervals to obtain a plurality of groups of sampling points, with the preset intervals of the groups of sampling points being different; performing processes on a current sampling point and the groups of sampling points to obtain data of arguments of complex numbers corresponding to the preset intervals; and determining an estimation value of a frequency offset of a current input signal according to the data of arguments of complex numbers corresponding to the preset intervals. The present disclosure further provides an apparatus for estimating a frequency offset, an electronic device and a computer-readable medium.

Abstract: Methods of treating subjects having G4C2 dipeptide repeat expansion in the gene C9ORF72, including subjects having amyotrophic lateral sclerosis or frontotemporal degeneration (ALS/FTD), are provided. Compounds directed at reducing the toxicity of G4C2 dipeptide repeat expansion in the gene C9ORF72 are described.

Abstract: The present invention discloses a method for fast cyclic redundancy check (CRC) encoding, and includes: mapping a CRC encoding generator polynomial to generate an (r+1)-order transfer matrix J; deleting a first row and a first column of said (r+1)-order transfer matrix J to obtain an r-order transfer matrix; forming a r×1 column matrix by first columns of 2nd to r+1th rows of said (r+1)-order transfer matrix; obtaining a zero input transfer matrix and a zero state transfer matrix of CRC encoding by the r-order transfer matrix and the r×1 column matrix; adding dummy bits before an input bit stream; and obtaining a CRC encoding check sequence according to the zero input transfer matrix, the zero state transfer matrix and the input bit stream after adding the dummy bits. The present invention further discloses an apparatus for fast cyclic redundancy check encoding.

Abstract: The present invention discloses a method for fast cyclic redundancy check (CRC) encoding, and includes: mapping a CRC encoding generator polynomial to generate an (r+1)-order transfer matrix J; deleting a first row and a first column of said (r+1)-order transfer matrix J to obtain an r-order transfer matrix; forming a r×1 column matrix by first columns of 2nd to r+1th rows of said (r+1)-order transfer matrix; obtaining a zero input transfer matrix and a zero state transfer matrix of CRC encoding by the r-order transfer matrix and the r×1 column matrix; adding dummy bits before an input bit stream; and obtaining a CRC encoding check sequence according to the zero input transfer matrix, the zero state transfer matrix and the input bit stream after adding the dummy bits. The present invention further discloses an apparatus for fast cyclic redundancy check encoding.