Patents by Inventor Shubhada H. Sahasrabudhe

Shubhada H. Sahasrabudhe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210280495
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first side of a die disposed on a first side of a substrate, and a cooling structure on a second side of the die, wherein the cooling structure comprises a first section attached to the substrate, and a second section disposed on a second side of the die, wherein the first and second sections are separated by an opening in the cooling structure. The opening surrounds a portion of the second section, and at least one flexure beam structure connects the first and second sections.
    Type: Application
    Filed: September 29, 2016
    Publication date: September 9, 2021
    Applicant: Intel Corporation
    Inventors: Siddarth Kumar, Shubhada H. Sahasrabudhe, Sandeep B. Sane, Shalabh Tandon
  • Publication number: 20200066654
    Abstract: Semiconductor packages having support members are provided. Support members can mitigate damage to a semiconductor die mounted on a semiconductor package. In some embodiments, an arrangement of support packages can be formed at respective locations of a frame layer that serves as a stiffener for the semiconductor package. Each support member in the arrangement can be formed from a same material of the frame layer or a different material. In some embodiments, a support member can be mounted or otherwise coupled to an exposed surface of the frame layer. In addition or in other embodiments, a support member can be mounted on a surface that supports the semiconductor die. The arrangement of support members can include support members comprising a first material and/or other support members formed from respective materials. A support member can be formed from a metal, a metal alloy, a semiconductor, a polymer, a composite material, or a porous material.
    Type: Application
    Filed: November 27, 2017
    Publication date: February 27, 2020
    Inventors: Je-Young CHANG, Shubhada H. SAHASRABUDHE, Tannaz HARIRCHIAN
  • Patent number: 10181432
    Abstract: Embodiments of the present disclosure provide techniques and configurations for a computing system with a thermal interface having magnetic particles. In some embodiments, the computing system may include a first part, a second part, and a thermal interface to couple the first and second parts. The thermal interface may comprise a thermal interface material having magnetic particles that are aligned in a defined direction relative to a surface of the first or second part, to provide desired thermal conductivity between the first and second parts. The defined direction of alignment of magnetic particles may comprise an alignment of the particles substantially perpendicularly to the surface of the first or second part. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Ameya Limaye, Shubhada H. Sahasrabudhe, Nachiket R. Raravikar
  • Publication number: 20180354443
    Abstract: A system and method for child car seat safety detection and notification are disclosed. A particular embodiment is configured to: provide at least one sensor to measure a condition present in an environment in which a child is restrained in a child car seat in a vehicle; determine, based on sensor data from the sensor, if the condition requires a notification to be sent to a user; generate a notification message including at least a portion of the sensor data and information indicative of a location of the child car seat; send the notification message to a mobile device application; and send the notification message to a vehicle subsystem application.
    Type: Application
    Filed: December 18, 2015
    Publication date: December 13, 2018
    Inventors: Nona Ebrahimi, Joseph M. Romeo, Christopher L. Ross, Rene J. Sanchez, Marcie M. Miller, Jill C. Sciarappo, Amarnath Kona, Shubhada H. Sahasrabudhe, Matthew J. Schneider, Rod E. Kronschnabel, Thomas V. Moss, Steven Whitehorn, Kevin Edwards, Keith A. Swesey, Cecilia Yancy, Camilo F. Gomez
  • Publication number: 20180269128
    Abstract: Embodiments of the present disclosure provide techniques and configurations for a computing system with a thermal interface having magnetic particles. In some embodiments, the computing system may include a first part, a second part, and a thermal interface to couple the first and second parts. The thermal interface may comprise a thermal interface material having magnetic particles that are aligned in a defined direction relative to a surface of the first or second part, to provide desired thermal conductivity between the first and second parts. The defined direction of alignment of magnetic particles may comprise an alignment of the particles substantially perpendicularly to the surface of the first or second part. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 16, 2017
    Publication date: September 20, 2018
    Inventors: Ameya Limaye, Shubhada H. Sahasrabudhe, Nachiket R. Raravikar
  • Publication number: 20180190596
    Abstract: Semiconductor packages having support members are provided. Support members can mitigate damage to a semiconductor die mounted on a semiconductor package. In some embodiments, an arrangement of support packages can be formed at respective locations of a frame layer that serves as a stiffener for the semiconductor package. Each support member in the arrangement can be formed from a same material of the frame layer or a different material. In some embodiments, a support member can be mounted or otherwise coupled to an exposed surface of the frame layer. In addition or in other embodiments, a support member can be mounted on a surface that supports the semiconductor die. The arrangement of support members can include support members comprising a first material and/or other support members formed from respective materials. A support member can be formed from a metal, a metal alloy, a semiconductor, a polymer, a composite material, or a porous material.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Je-Young G. Chang, Shubhada H. Sahasrabudhe, Tannaz Harirchian
  • Patent number: 9953934
    Abstract: A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along the substrate. A plurality of electrical contacts extend between at least the device and the substrate. One or more counter moment elements are coupled with the substrate. The one or more counter moment elements include a passive configuration and a counter moment configuration. In the counter moment configuration the one or more counter moment elements are configured to apply a counter moment to the substrate to counteract the warped configuration. In the passive configuration the one or more counter moment elements are configured to apply a neutral counter moment less than the counter moment of the counter moment configuration.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Siddarth Kumar, Sandeep B Sane, Shubhada H. Sahasrabudhe, Shalabh Tandon
  • Publication number: 20170178987
    Abstract: A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along the substrate. A plurality of electrical contacts extend between at least the device and the substrate. One or more counter moment elements are coupled with the substrate. The one or more counter moment elements include a passive configuration and a counter moment configuration. In the counter moment configuration the one or more counter moment elements are configured to apply a counter moment to the substrate to counteract the warped configuration. In the passive configuration the one or more counter moment elements are configured to apply a neutral counter moment less than the counter moment of the counter moment configuration.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 22, 2017
    Inventors: Siddarth Kumar, Sandeep B. Sane, Shubhada H. Sahasrabudhe, Shalabh Tandon
  • Patent number: 9659908
    Abstract: Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Shubhada H. Sahasrabudhe, Sandeep B Sane, Siddarth Kumar, Shalabh Tandon
  • Publication number: 20170133350
    Abstract: Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 11, 2017
    Inventors: Shubhada H. Sahasrabudhe, Sandeep B. Sane, Siddarth Kumar, Shalabh Tandon
  • Patent number: 9368461
    Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: June 14, 2016
    Assignee: INTEL CORPORATION
    Inventors: Sven Albers, Georg Seidemann, Sonja Koller, Stephan Stoeckl, Shubhada H. Sahasrabudhe, Sandeep B. Sane
  • Patent number: 9299672
    Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: March 29, 2016
    Assignee: INTEL CORPORATION
    Inventors: Sven Albers, Georg Seidemann, Sonja Koller, Stephan Stoeckl, Shubhada H. Sahasrabudhe, Sandeep B. Sane
  • Publication number: 20150333022
    Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 19, 2015
    Inventors: Sven Albers, Georg Seidemann, Sonja Koller, Stephan Stoeckl, Shubhada H. Sahasrabudhe, Sandeep B. Sane
  • Patent number: 7411296
    Abstract: A method, system, and apparatus, the apparatus including a metal layer on silicon, photo-resist material disposed on the metal layer, a bump pad reservoir adjacent to the metal layer, a quantity of interconnect metal disposed in the bump pad reservoir, and a resist opening in resist material disposed on a surface of the bump metal and adjacent the interconnect metal. The resist opening may be wider at an open end thereof than at an end in contact with the interconnect metal.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: August 12, 2008
    Assignee: Intel Corporation
    Inventors: Shubhada H. Sahasrabudhe, Nitin A. Deshpande