Patents by Inventor SHUBHAM RAJPUT

SHUBHAM RAJPUT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selection of full or incremental implementation flows in processing circuit designs
    Patent number: 11983478
    Abstract: A machine learning-based process includes identifying a first set of features that includes features of a reference implementation of a circuit design and features of a synthesized version of a modified version of the circuit design. A first classification model is applied to the first set of features, and the first classification model indicates a full implementation flow or an incremental implementation flow. The full implementation flow is performed on the synthesized version of the modified version in response to the first classification model indicating the full implementation flow, and the incremental implementation flow is performed on the synthesized version of the modified version in response to the first classification model indicating the incremental implementation flow. The full and incremental implementation flows generate implementation data that is suitable for making an integrated circuit (IC).
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: May 14, 2024
    Assignee: XILINX, INC.
    Inventors: Shant Chandrakar, Sourabh Anand, Shubham Rajput, Kameshwar Chandrasekar
  • SELECTION OF FULL OR INCREMENTAL IMPLEMENTATION FLOWS IN PROCESSING CIRCUIT DESIGNS
    Publication number: 20230289503
    Abstract: A machine learning-based process includes identifying a first set of features that includes features of a reference implementation of a circuit design and features of a synthesized version of a modified version of the circuit design. A first classification model is applied to the first set of features, and the first classification model indicates a full implementation flow or an incremental implementation flow. The full implementation flow is performed on the synthesized version of the modified version in response to the first classification model indicating the full implementation flow, and the incremental implementation flow is performed on the synthesized version of the modified version in response to the first classification model indicating the incremental implementation flow. The full and incremental implementation flows generate implementation data that is suitable for making an integrated circuit (IC).
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Applicant: Xilinx, Inc.
    Inventors: SHANT CHANDRAKAR, SOURABH ANAND, SHUBHAM RAJPUT, KAMESHWAR CHANDRASEKAR