Patents by Inventor Shuen-Shin Liang

Shuen-Shin Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210376103
    Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG
  • Publication number: 20210359125
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple channel structures suspended over a semiconductor substrate. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the channel structures. The semiconductor device structure further includes a gate stack wrapping around the channel structures. In addition, the semiconductor device structure includes a conductive contact wrapping around terminals of the epitaxial structures.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Pang-Yen TSAI, Keng-Chu LIN, Sung-Li WANG, Pinyen LIN
  • Publication number: 20210335720
    Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.
    Type: Application
    Filed: January 5, 2021
    Publication date: October 28, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG
  • Patent number: 11158539
    Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature; etching a hole through the dielectric layer and exposing the conductive feature; depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature; depositing a second metal over the first metal; and annealing the structure including the first and the second metals.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Hung-Yi Huang, Yu-Yun Peng, Mrunal A. Khaderbad, Chia-Hung Chu, Shuen-Shin Liang, Keng-Chu Lin
  • Publication number: 20210233861
    Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.
    Type: Application
    Filed: July 22, 2020
    Publication date: July 29, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsu-Kai Chang, Keng-Chu Lin, Sung-Li Wang, Shuen-Shin Liang, Chia-Hung Chu
  • Publication number: 20210202399
    Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.
    Type: Application
    Filed: July 31, 2020
    Publication date: July 1, 2021
    Inventors: Cheng-Wei CHANG, Chia-Hung CHU, Kao-Feng LIN, Hsu-Kai CHANG, Shuen-Shin LIANG, Sung-Li WANG, Yi-Ying LIU, Po-Nan YEH, Yu Shih WANG, U-Ting CHIU, Chun-Neng LIN, Ming-Hsi YEH
  • Publication number: 20210193506
    Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.
    Type: Application
    Filed: July 23, 2020
    Publication date: June 24, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chen-Han WANG, Keng-Chu LIN, Tetsuji UENO, Ting-Ting CHEN
  • Publication number: 20210193798
    Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.
    Type: Application
    Filed: July 23, 2020
    Publication date: June 24, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin Liang, Chen-Han Wang, Keng-Chu Lin, Tstsuji Ueno, Ting-Ting Chen
  • Publication number: 20210193511
    Abstract: A multi-layer interconnect structure with a self-aligning barrier structure and a method for fabricating the same is disclosed. For example, the method includes forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure, pre-cleaning the via with a metal halide, forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide, and depositing a second metal in the via on top of the barrier structure.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li WANG, Shuen-Shin LIANG, Yu-Yun PENG, Fang-Wei LEE, Chia-Hung CHU, Mrunal Abhijith KHADERBAD, Keng-Chu LIN
  • Publication number: 20210193799
    Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.
    Type: Application
    Filed: November 20, 2020
    Publication date: June 24, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chen-Han WANG, Keng-Chu LIN, Tetsuji UENO, Ting-Ting CHEN
  • Patent number: 11011413
    Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Shuen-Shin Liang, Jung-Hao Chang, Chia-Hung Chu, Keng-Chu Lin
  • Publication number: 20210098295
    Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature; etching a hole through the dielectric layer and exposing the conductive feature; depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature; depositing a second metal over the first metal; and annealing the structure including the first and the second metals.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Sung-Li Wang, Hung-Yi Huang, Yu-Yun Peng, Mrunal A. Khaderbad, Chia-Hung Chu, Shuen-Shin Liang, Keng-Chu Lin
  • Publication number: 20200273794
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate stack and a first dielectric layer over the substrate, a source/drain (S/D) region, a contact, and a via. The first dielectric layer is laterally aside and over the gate stack. The S/D region is located in the substrate on sides of the gate stack. The contact penetrates through the first dielectric layer to electrically connect to the S/D region. The via penetrates through a second dielectric layer to connect to the contact. The via includes a conductive layer and an adhesion promoter layer on sidewalls of the conductive layer. The conductive layer is in contact with the contact.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal A. Khaderbad, Keng-Chu Lin, Sung-Li Wang, Shuen-Shin Liang, Yasutoshi Okuno, Yu-Yun Peng, Chia-Hung Chu
  • Publication number: 20200273695
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a dielectric structure on a semiconductor substrate, introducing a first gas on the dielectric structure to form first conductive structures on the dielectric structure, and introducing a second gas on the first conductive structures and the dielectric structure. The second gas is different from the first gas. The method also includes introducing a third gas on the first conductive structures and the dielectric structure to form second conductive structures on the dielectric structure. The first gas and the third gas include the same metal.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal A. KHADERBAD, Keng-Chu LIN, Shuen-Shin LIANG, Sung-Li WANG, Yasutoshi OKUNO, Yu-Yun PENG
  • Publication number: 20200098616
    Abstract: Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.
    Type: Application
    Filed: March 25, 2019
    Publication date: March 26, 2020
    Inventors: Chih-Tang Peng, Shuen-Shin Liang, Keng-Chu Lin, Teng-Chun Tsai
  • Publication number: 20190214296
    Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.
    Type: Application
    Filed: March 15, 2019
    Publication date: July 11, 2019
    Inventors: Sung-Li Wang, Shuen-Shin Liang, Jung-Hao Chang, Chia-Hung Chu, Keng-Chu Lin