Abstract: An address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality of interleaving addresses according to a QPP function ?(i)=(f1i+f2i2) mod k, where f1 and f2 are QPP coefficients, k is information block length of an input sequence, 0?i?k?1, and mod is a modulus operation. Each of the plurality of QPP units is a parallel computation unit, and outputs in parallel a corresponding group of interleaver addresses, where ?(i) is also a ith interleaving address generated by the apparatus.

Abstract: An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver is provided. It comprises a basic recursive unit, and L recursive units represented by first recursive unit up to Lth recursive units. The apparatus inputs a plurality of configurable parameters according to a QPP function ?(i)=(f1i+f2i2) mod k, generates a plurality of interleaver addresses in serial via the basic recursive unit, and generates L groups of corresponding interleaver addresses via the first up to the Lth recursive units, wherein ?(i) is the i-th interleaver address generated by the apparatus, f1 and f2 are QPP coefficients, and k is information block length of an input sequence, 0?i?k?1.

Abstract: An address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality of interleaving addresses according to a QPP function ?(i)=(f1i+f2i2) mod k, where f1 and f2 are QPP coefficients, k is information block length of an input sequence, 0?i?k?1, and mod is a modulus operation. Each of the plurality of QPP units is a parallel computation unit, and outputs in parallel a corresponding group of interleaver addresses, where ?(i) is also a ith interleaving address generated by the apparatus.

Abstract: A multiplexing method for data switching is disclosed. In the method, a continuous data is received, and the continuous data includes a plurality of super frames, and each super frame includes a plurality of frames. These super frames are divided into a set of even super frames and a set of odd super frames. The frames included in the set of odd super frames are sorted by corresponding required bit error rate of each frame decreasingly or increasingly. The frames included in the set of even super frames are sorted by the required bit error rate of each frame increasingly or decreasingly. An encoder is used to encode these sorted super frames.

Abstract: An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver is provided. It comprises a basic recursive unit, and L recursive units represented by first recursive unit up to Lth recursive units. The apparatus inputs a plurality of configurable parameters according to a QPP function ?(i)=(f1i+f2i2) mod k, generates a plurality of interleaver addresses in serial via the basic recursive unit, and generates L groups of corresponding interleaver addresses via the first up to the Lth recursive units, wherein ?(i) is the i-th interleaver address generated by the apparatus, f1 and f2 are QPP coefficients, and k is information block length of an input sequence, 0?i?k?1.

Abstract: A decoder suitable for use in a digital communications system utilizing an RS(n?, k?) code modified from an RS(n, k) code receives n?-symbol vectors each including k? message symbols and r?=n??k? parity symbols and decodes the n?-symbol vectors to correct errors therein, wherein n, k, n?, and k? are integers, and k?<n?<n, k?<k<n, and wherein the decoder stores therein one erasure locator polynomial ?0(x). The decoder includes a syndrome calculator for receiving the n?-symbol vectors and for calculating syndromes of each n?-symbol vector, wherein the i-th syndrome Si of one n?-symbol vector R?, (rn??1, rn??2, . . . , r0), is Si=Rs(?i+1) for i=0, 1, . . . , n?k?1, wherein Rs(x)=rn??1xn??1+rn??2xn??2+ . . . +r0, and means for finding the locations and values of the errors in each n?-symbol vector using the syndromes thereof and the one erasure locator polynomial ?0(x).

Abstract: A multiplexing method for data switching is disclosed. In the method, a continuous data is received, and the continuous data includes a plurality of super frames, and each super frame includes a plurality of frames. These super frames are divided into a set of even super frames and a set of odd super frames. The frames included in the set of odd super frames are sorted by corresponding required bit error rate of each frame decreasingly or increasingly. The frames included in the set of even super frames are sorted by the required bit error rate of each frame increasingly or decreasingly. An encoder is used to encode these sorted super frames.

Abstract: A decoder suitable for use in a digital communications system utilizing an RS(n?, k?) code modified from an RS(n, k) code receives n?-symbol vectors each including k? message symbols and r?=n?-k? parity symbols and decodes the n?-symbol vectors to correct errors therein, wherein n, k, n?, and k? are integers, and k?<n?<n, k?<k<n, and wherein the decoder stores therein one erasure locator polynomial ?0(x). The decoder includes a syndrome calculator for receiving the n?-symbol vectors and for calculating syndromes of each n?-symbol vector, wherein the i-th syndrome Si of one n?-symbol vector R?, (rn??1, rn??2, . . . , r0), is Si=Rs(?i+1) for i=0, 1, . . . , n?k?1, wherein Rs(x)=rn??1xn??1+rn??2xn??2+ . . . +r0, and means for finding the locations and values of the errors in each n?-symbol vector using the syndromes thereof and the one erasure locator polynomial ?0(x).