Abstract: A shielded gate MOSFET device and a manufacturing method thereof is provided. In the method, the shielded gate thick dielectric layers are formed with the thick oxide layer process at the bottoms in the trenches, poly is deposited in each trench and is back etched to leave gate poly on the side wall of each trench, whereas the portion, right in the center of each trench, of the thin poly layer is removed to be filled with the contact hole dielectric layer, which achieves the effect of streamlining the process flow.

Abstract: A shield gate trench MOSFET device includes a substrate and a trench in the substrate. A lower portion of the trench is filled with a shield gate dielectric layer and a first polysilicon layer. An upper portion of the trench is filled with a first dielectric layer, a second polysilicon layer, and a second dielectric layer. The second dielectric layer is located above the second polysilicon layer, and the top of the second polysilicon layer is lower than the surface of the substrate. A well region is located outside the trench, and a Schottky implantation region is located outside the well region. The bottom of the Schottky implantation region is higher than the bottom of the well region. The well region includes a source region and a well contact region. The well contact region is located between the source region and the Schottky implantation region.

Abstract: Trench gate power MOSFET with an on-region. Cells in the on-region include a first epitaxial layer and a channel region. First trenches corresponding to polysilicon gates penetrate through the channel region, and each polysilicon gate is etched to form a groove in the top, the grooves filled with an interlayer film. A source region formed on side faces of the grooves in a self-aligned mode through angled ion implantation. Through the source region of a side structure, the surface of a portion, between the first trenches, of the channel region is directly exposed and formed with a well contact region. A front metal layer is formed on the surfaces of the cells in the on-region and leads out a source. The front metal layer of the source directly makes contact with well contact region and source region to form a connection structure without contact holes.

Abstract: Trench gate power MOSFET with an on-region. Cells in the on-region include a first epitaxial layer and a channel region. First trenches corresponding to polysilicon gates penetrate through the channel region, and each polysilicon gate is etched to form a groove in the top, the grooves filled with an interlayer film. A source region formed on side faces of the grooves in a self-aligned mode through angled ion implantation. Through the source region of a side structure, the surface of a portion, between the first trenches, of the channel region is directly exposed and formed with a well contact region. A front metal layer is formed on the surfaces of the cells in the on-region and leads out a source. The front metal layer of the source directly makes contact with well contact region and source region to form a connection structure without contact holes.