Abstract: The present specification relates to a battery, comprising an anode, a cathode, an electrolyte disposed between the anode and the cathode, a halogen in contact with the cathode, and a metal in contact with the anode, wherein the halogen is in contact with a polymeric halogen sequestering agent (HSA) which is a polymer comprising a moiety capable of sequestering the halogen.

Abstract: Disclosed are a semiconductor device and a preparation method thereof. The semiconductor device includes a substrate, a multilayer semiconductor layer, a dielectric layer, a source and a drain. A gate trench is formed in the multilayer semiconductor layer and the dielectric layer. A gate is formed in the gate trench, and the gate trench includes a first sub-portion of the gate trench formed in the multilayer semiconductor layer and a second sub-portion of the gate trench penetrating the dielectric layer. The second sub-portion of the gate trench includes a second opening located on the surface of the dielectric layer close to the substrate and a third opening on the surface of the dielectric layer away from the substrate. The vertical projection of the third opening on the substrate covers the vertical projection of the second opening on the substrate.

Abstract: The present specification relates to a battery, comprising an anode, a cathode, an electrolyte disposed between the anode and the cathode, a halogen in contact with the cathode, and a metal in contact with the anode, wherein the halogen is in contact with a polymeric halogen sequestering agent (HSA) which is a polymer comprising a moiety capable of sequestering the halogen.

Abstract: A semiconductor packaging structure for packaging a semiconductor chip is disclosed, the semiconductor chip comprises at least two electrodes, each of the at least two electrodes comprises at least one electrode opening, and the packaging structure comprises: a packaging chassis, provided with at least two pin electrodes respectively corresponding to the at least two electrodes; and at least two extended electrodes, each of the at least two extended electrodes being electrically connected to one of the at least two pin electrodes, and comprising at least one conductive pillar for inserting into the at least one electrode opening formed on one of the at least two electrodes.

Abstract: A semiconductor packaging structure for packaging a semiconductor chip is disclosed, the semiconductor chip comprises at least two electrodes, each of the at least two electrodes comprises at least one electrode opening, and the packaging structure comprises: a packaging chassis, provided with at least two pin electrodes respectively corresponding to the at least two electrodes; and at least two extended electrodes, each of the at least two extended electrodes being electrically connected to one of the at least two pin electrodes, and comprising at least one conductive pillar for inserting into the at least one electrode opening formed on one of the at least two electrodes.

Abstract: A semiconductor package structure comprises: a high-voltage depletion type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a low-voltage enhancement type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a shell comprising a cavity for receiving the high-voltage depletion type semiconductor transistor and the low-voltage enhancement type semiconductor transistor, and a high-voltage terminal, a first low-voltage terminal and a second low-voltage terminal; and cascade circuits comprising a supporting sheet having a conductive surface. The source electrode of the high-voltage depletion type transistor and the drain electrode of the low-voltage enhancement type semiconductor transistor are fixed to the conductive surface of the supporting sheet and electrically connected to each other through the conductive surface of the supporting sheet.

Abstract: A semiconductor package structure comprises: a high-voltage depletion type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a low-voltage enhancement type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a shell comprising a cavity for receiving the high-voltage depletion type semiconductor transistor and the low-voltage enhancement type semiconductor transistor, and a high-voltage terminal, a first low-voltage terminal and a second low-voltage terminal; and cascade circuits comprising a supporting sheet having a conductive surface. The source electrode of the high-voltage depletion type transistor and the drain electrode of the low-voltage enhancement type semiconductor transistor are fixed to the conductive surface of the supporting sheet and electrically connected to each other through the conductive surface of the supporting sheet.

Abstract: A mold die includes a side wall forming a hollow cavity and opposing first and second axial ends. The side wall has first and second openings respectively at the first and second axial ends. Each of the first and second openings accesses the hollow cavity. A main wall is coupled to the side wall at the first end thereof and spans the first opening. A center of the main wall is aligned with a longitudinal axis of the side wall. The main wall defines a plane oriented generally perpendicularly with respect to the longitudinal axis of the side wall. First and second gates are formed through the main wall to access the hollow cavity. The first and second gates define a first line lying in the plane of the main wall. The center of the main wall is located on the first line between the first and second gates.

Abstract: Forming a packaged semiconductor device includes placing a semiconductor die attached to a carrier into a mold cavity having an injection port, wherein the semiconductor die has an encapsulant exclusion region on a top surface of the semiconductor die within an outer perimeter of the top surface; and flowing an encapsulant over the semiconductor die and carrier from the injection port, wherein the encapsulant flows around the encapsulant exclusion region to surround the encapsulant exclusion region without covering the encapsulant exclusion region. The encapsulant exclusion region has a first length corresponding to a single longest distance across the encapsulant exclusion region, wherein the first length is aligned, within 30 degrees, to a line defined by a shortest distance between an entry point of the injection port into the mold cavity and an outer perimeter of the encapsulant exclusion region.

Abstract: Forming a packaged semiconductor device includes placing a semiconductor die attached to a carrier into a mold cavity having an injection port, wherein the semiconductor die has an encapsulant exclusion region on a top surface of the semiconductor die within an outer perimeter of the top surface; and flowing an encapsulant over the semiconductor die and carrier from the injection port, wherein the encapsulant flows around the encapsulant exclusion region to surround the encapsulant exclusion region without covering the encapsulant exclusion region. The encapsulant exclusion region has a first length corresponding to a single longest distance across the encapsulant exclusion region, wherein the first length is aligned, within 30 degrees, to a line defined by a shortest distance between an entry point of the injection port into the mold cavity and an outer perimeter of the encapsulant exclusion region.

Abstract: A lead frame for a quad flat no-lead (QFN) type semiconductor device package includes a die pad, a plurality of leads that surround the die pad. The outer edge of leads includes a channel that extends from a lower surface to an upper surface of the leads. A semiconductor die is attached to the die pad. An inner edge of each lead is electrically connected to a corresponding bonding pad on the semiconductor die. The assembly is covered with an encapsulation material except that the outer edge of each lead and the corresponding channel are exposed. The channel allows solder to flow up the outer edge of a lead when the QFN device is soldered to a substrate, which improves the ability to perform visual inspection of the solder-lead connection.

Abstract: A lead frame for reducing detrimental effects of burr formation includes a lead frame that has leads where a portion of a top surface is removed from a first lead and a portion of a bottom surface is removed from a second lead adjacent to the first lead to reduce spacing between leads while reducing the detrimental effects of burr formation, such as shorting and the like, caused during singulation of a semiconductor device manufactured with the lead frame.

Abstract: A lead frame for reducing detrimental effects of burr formation includes a lead frame that has leads where a portion of a top surface is removed from a first lead and a portion of a bottom surface is removed from a second lead adjacent to the first lead to reduce spacing between leads while reducing the detrimental effects of burr formation, such as shorting and the like, caused during singulation of a semiconductor device manufactured with the lead frame.

Abstract: A lead frame for providing electrical interconnection to a semiconductor die has a generally rectangular flag area having first and second major surfaces and four sides. The flag area is sized and shaped to receive a semiconductor die on one of the first and second major surfaces. A first row of leads is located adjacent to a first one of the four sides of the flag area and a second row of leads is located adjacent to a second one of the four sides of the flag area, where the second one of the four sides is adjacent to the first one of the four sides. The remaining two sides do not have any adjacent leads.