Abstract: A first spring array and a second spring array are provided in a holder body. Three sample plates can be mounted in the holder body. On each sample plate, pressing-up forces from the first spring array and the second spring array are applied, but upward movement of each sample plate is restricted by an inner surface of a cover.

Abstract: A first spring array and a second spring array are provided in a holder body. Three sample plates can be mounted in the holder body. On each sample plate, pressing-up forces from the first spring array and the second spring array are applied, but upward movement of each sample plate is restricted by an inner surface of a cover.

Abstract: A protection IC includes a bias output terminal connected to a back gate of a MOS transistor, a load side terminal connected to a power supply path between a load and the MOS transistor, a load side switch inserted in an electric current path connecting the bias output terminal and the load side terminal, and a control circuit configured to control the load side switch based on a state of a secondary battery and thereby cause a back gate control signal for controlling a voltage of the back gate to be output from the bias output terminal. The load side switch is formed on an N-type silicon substrate and includes at least two NMOS transistors whose drains are connected to each other, and the control circuit is configured to simultaneously turn on or turn off the two NMOS transistors based on the state of the secondary battery.

Abstract: A battery protection integrated circuit for protecting a secondary battery by controlling a charge or discharge operation of the secondary battery includes a power supply terminal connected to a positive electrode of the secondary battery; a ground terminal connected to a negative electrode of the secondary battery; an input terminal connected to a negative terminal coupled to ground of a load; a control terminal at which a control signal is input, wherein the control signal has a voltage level with reference to a potential at the negative terminal; a signal detection circuit configured to detect a relative voltage level of the control signal input at the control terminal with reference to a potential at the input terminal; and a control circuit configured to control open/close of a switching circuit connected to a charge or discharge path between the negative electrode and the negative terminal based on the control signal.

Abstract: A secondary battery protection circuit includes a first terminal connected to a power supply path between a secondary battery and a MOS transistor, a second terminal connected to the power supply path between a load and the MOS transistor, a third terminal connected to a gate of the MOS transistor, a fourth terminal connected to a back gate of the MOS transistor, a control circuit that outputs a switch control signal based on a detected abnormal state of the secondary battery, and a switch control circuit including a first switch for connecting the fourth terminal with the first terminal and a second switch for connecting the fourth terminal with the second terminal. At least one of the resistance between the fourth terminal and the first terminal and the resistance between the fourth terminal and the second terminal is greater than the on resistance value of the MOS transistor.

Abstract: A protection IC includes a bias output terminal connected to a back gate of a MOS transistor, a load side terminal connected to a power supply path between a load and the MOS transistor, a load side switch inserted in an electric current path connecting the bias output terminal and the load side terminal, and a control circuit configured to control the load side switch based on a state of a secondary battery and thereby cause a back gate control signal for controlling a voltage of the back gate to be output from the bias output terminal. The load side switch is formed on an N-type silicon substrate and includes at least two NMOS transistors whose drains are connected to each other, and the control circuit is configured to simultaneously turn on or turn off the two NMOS transistors based on the state of the secondary battery.

Abstract: A secondary battery protection circuit includes a first terminal connected to a power supply path between a secondary battery and a MOS transistor, a second terminal connected to the power supply path between a load and the MOS transistor, a third terminal connected to a gate of the MOS transistor, a fourth terminal connected to a back gate of the MOS transistor, a control circuit that outputs a switch control signal based on a detected abnormal state of the secondary battery, and a switch control circuit including a first switch for connecting the fourth terminal with the first terminal and a second switch for connecting the fourth terminal with the second terminal. At least one of the resistance between the fourth terminal and the first terminal and the resistance between the fourth terminal and the second terminal is greater than the on resistance value of the MOS transistor.

Abstract: A battery protection integrated circuit for protecting a secondary battery by controlling a charge or discharge operation of the secondary battery includes a power supply terminal connected to a positive electrode of the secondary battery; a ground terminal connected to a negative electrode of the secondary battery; an input terminal connected to a negative terminal coupled to ground of a load; a control terminal at which a control signal is input, wherein the control signal has a voltage level with reference to a potential at the negative terminal; a signal detection circuit configured to detect a relative voltage level of the control signal input at the control terminal with reference to a potential at the input terminal; and a control circuit configured to control open/close of a switching circuit connected to a charge or discharge path between the negative electrode and the negative terminal based on the control signal.

Abstract: A communication device, includes a CMOS type inverter configured to transfer a signal, the signal being transferred and received between an electronic device and a control part able to communicate with the electronic device whose electric power supply is a rechargeable battery; and a regulator configured to generate a regulated voltage, the regulated voltage being formed by decreasing an electric power supply voltage of the electronic device, wherein the regulator includes a depletion type NMOS transistor where a drain is connected to a high electric potential side of the electric power supply voltage and a gate and a source are mutually connected, and a capacitive element having an electrode connected to the source side and another electrode connected to a low electric potential side of the electric power supply voltage, wherein a voltage of the capacitive element is supplied across both ends of the inverter.

Abstract: In a semiconductor integrated circuit arranged to perform sag compensation for a video signal, an operational amplifier includes a non-inverted input terminal, an inverted input terminal, and an output terminal, in which a video signal is input to the non-inverted input terminal. A first resistor includes a first end connected to the inverted input terminal and a second end being grounded. The output terminal is connected to a first external terminal and the inverted input terminal is connected to a second external terminal. A second resistor includes a first end connected to the output terminal and a second end connected to the inverted input terminal. A first capacitor is disposed between the first external terminal and the second external terminal and connected in parallel to the second resistor, and the second resistor has a resistance value determined based on a capacitance value of the first capacitor.

Abstract: A communication device includes a first JK flip-flop (FF) outputting a first output signal in response to a first input signal at a J-input and a reversed signal of the first input signal at a K-input, and a second JK FF outputting a second output signal in response to a second input signal at a J-input and a reversed signal of the second input signal at a K-input. A clock input to a NAND gate (12) is replaced by a reversed signal of a Q-output of the second JK FF. A clock input to a NAND gate (13) is replaced by the reversed signal of the second input signal. A clock input to a NAND gate (22) is replaced by a reversed signal of a Q-output of the first JK FF. A clock input to a NAND gate (23) is replaced by the reversed signal of the first input signal.

Abstract: A communication device includes a first JK flip-flop (FF) outputting a first output signal in response to a first input signal at a J-input and a reversed signal of the first input signal at a K-input, and a second JK FF outputting a second output signal in response to a second input signal at a J-input and a reversed signal of the second input signal at a K-input. A clock input to a NAND gate (12) is replaced by a reversed signal of a Q-output of the second JK FF. A clock input to a NAND gate (13) is replaced by the reversed signal of the second input signal. A clock input to a NAND gate (22) is replaced by a reversed signal of a Q-output of the first JK FF. A clock input to a NAND gate (23) is replaced by the reversed signal of the first input signal.

Abstract: A communication device, includes a CMOS type inverter configured to transfer a signal, the signal being transferred and received between an electronic device and a control part able to communicate with the electronic device whose electric power supply is a rechargeable battery; and a regulator configured to generate a regulated voltage, the regulated voltage being formed by decreasing an electric power supply voltage of the electronic device, wherein the regulator includes a depletion type NMOS transistor where a drain is connected to a high electric potential side of the electric power supply voltage and a gate and a source are mutually connected, and a capacitive element having an electrode connected to the source side and another electrode connected to a low electric potential side of the electric power supply voltage, wherein a voltage of the capacitive element is supplied across both ends of the inverter.

Abstract: A disclosed reset device for outputting a reset signal based on a magnitude of an input power supply voltage includes: a power supply voltage monitoring unit including a comparator to which a detection voltage detected based on the magnitude of the power supply voltage and a reference voltage to be used as an inversion reference for the reset signal are input, the comparator comparing the detection voltage with the reference voltage and outputting an output voltage in accordance with a result of the comparison; and a reset signal outputting unit including a CMOS inverter to which the output voltage output from the power supply voltage monitoring unit is input, the unit outputting the reset signal. An impedance unit is disposed between a P-channel MOS transistor constituting the inverter and a power supply voltage line and/or between an N-channel MOS transistor constituting the inverter and a ground line.

Abstract: In a semiconductor integrated circuit arranged to perform sag compensation for a video signal, an operational amplifier includes a non-inverted input terminal, an inverted input terminal, and an output terminal, in which a video signal is input to the non-inverted input terminal. A first resistor includes a first end connected to the inverted input terminal and a second end being grounded. The output terminal is connected to a first external terminal and the inverted input terminal is connected to a second external terminal. A second resistor includes a first end connected to the output terminal and a second end connected to the inverted input terminal. A first capacitor is disposed between the first external terminal and the second external terminal and connected in parallel to the second resistor, and the second resistor has a resistance value determined based on a capacitance value of the first capacitor.

Abstract: A battery protection device protects a battery from an abnormal state. The battery protection device includes a detector that detects an abnormality of the battery and outputs an abnormality detection signal when the abnormality is detected. A current is input to an input terminal from outside. A voltage converter converts the current input to the input terminal to voltage and outputs the voltage. A combiner combines the abnormality detection signal with the voltage and outputs a combined signal. A current converter converts the combined signal to a current. An output terminal outputs the current.

Abstract: A disclosed reset device for outputting a reset signal based on a magnitude of an input power supply voltage includes: a power supply voltage monitoring unit including a comparator to which a detection voltage detected based on the magnitude of the power supply voltage and a reference voltage to be used as an inversion reference for the reset signal are input, the comparator comparing the detection voltage with the reference voltage and outputting an output voltage in accordance with a result of the comparison; and a reset signal outputting unit including a CMOS inverter to which the output voltage output from the power supply voltage monitoring unit is input, the unit outputting the reset signal. An impedance unit is disposed between a P-channel MOS transistor constituting the inverter and a power supply voltage line and/or between an N-channel MOS transistor constituting the inverter and a ground line.

Abstract: A battery protection device protects a battery from an abnormal state. The battery protection device includes a detector that detects an abnormality of the battery and outputs an abnormality detection signal when the abnormality is detected. A current is input to an input terminal from outside. A voltage converter converts the current input to the input terminal to voltage and outputs the voltage. A combiner combines the abnormality detection signal with the voltage and outputs a combined signal. A current converter converts the combined signal to a current. An output terminal outputs the current.

Abstract: A data writing system capable of writing data in at least one electrically rewritable ROM mounted on target board, comprising: a transportation unit for transporting the target board to a predetermined writing position at which data is to be written, a data writing unit for writing data in the ROM mounted on the target board, and a connection unit for electrically connecting the ROM mounted on the target board at the predetermined writing position with the data writing unit through at least one transmission line extending from the ROM.

Abstract: A data writing system capable of writing data in at least one electrically rewritable ROM mounted on target board, comprising: