Patents by Inventor Shuhei Horimoto

Shuhei Horimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170287869
    Abstract: A method of connecting a wire with a terminal including a plurality of conductors is provided. The method includes: positioning the terminal by holding a part of the terminal between an upper side jig and a lower side jig; and connecting the wire and one of a plurality of conductors, which is exposed on a surface of the positioned terminal. The terminal includes a laminate structure that includes an insulator interposed between a first conductor and a second conductor. The part of the terminal held in the positioning of the terminal includes a pressure receiving area, where a contact area between the upper side jig and an upper surface of the terminal and a contact area between the lower side jig and a lower surface of the terminal overlap. The laminate structure exists outside of the pressure receiving area, and does not exist in the pressure receiving area.
    Type: Application
    Filed: June 19, 2017
    Publication date: October 5, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Shuhei HORIMOTO
  • Patent number: 9716077
    Abstract: A method of connecting a wire with a terminal including a plurality of conductors is provided. The method includes: positioning the terminal by holding a part of the terminal between an upper side jig and a lower side jig; and connecting the wire and one of a plurality of conductors, which is exposed on a surface of the positioned terminal. The terminal includes a laminate structure that includes an insulator interposed between a first conductor and a second conductor. The part of the terminal held in the positioning of the terminal includes a pressure receiving area, where a contact area between the upper side jig and an upper surface of the terminal and a contact area between the lower side jig and a lower surface of the terminal overlap. The laminate structure exists outside of the pressure receiving area, and does not exist in the pressure receiving area.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: July 25, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Shuhei Horimoto
  • Publication number: 20170077063
    Abstract: A method of connecting a wire with a terminal including a plurality of conductors is provided. The method includes: positioning the terminal by holding a part of the terminal between an upper side jig and a lower side jig; and connecting the wire and one of a plurality of conductors, which is exposed on a surface of the positioned terminal. The terminal includes a laminate structure that includes an insulator interposed between a first conductor and a second conductor. The part of the terminal held in the positioning of the terminal includes a pressure receiving area, where a contact area between the upper side jig and an upper surface of the terminal and a contact area between the lower side jig and a lower surface of the terminal overlap. The laminate structure exists outside of the pressure receiving area, and does not exist in the pressure receiving area.
    Type: Application
    Filed: August 3, 2016
    Publication date: March 16, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Shuhei HORIMOTO
  • Patent number: 9496214
    Abstract: Power electronics devices having thermal stress reduction elements are disclosed. A power electronics device includes a heat source having a heat source perimeter, a first conduction member coupled to the heat source, and a substrate coupled to the first conduction member. The first conduction member includes a support portion that extends to at least the heat source perimeter and a plurality of finger portions extending from the support portion and separated from one another by web regions, where the plurality of finger portions have a finger thickness that is greater than a web thickness of the web regions.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: November 15, 2016
    Assignee: Toyota Motor Engineering & Manufacturing North American, Inc.
    Inventors: Tsuyoshi Nomura, Sang Won Yoon, Ercan Mehmet Dede, Shuhei Horimoto
  • Patent number: 8921989
    Abstract: Power electronics modules having solder layers with reduced thermal-stress are disclosed. In one embodiment, a power electronics module includes a power electronics device having a first surface, a second surface, a first edge, and a second edge opposite the first edge. The power electronics device has a device length measured from the first edge to the second edge. A first solder layer is adjacent to the first surface of the power electronics device, and a second solder layer is adjacent to the second surface. The first solder layer and the second solder layer have a maximum thickness T along a length that is less than the device length of the power electronics device. A first thermally conductive layer is adjacent to the first solder layer, and a second thermally conductive layer is adjacent to the second solder layer. In some embodiments, the first and second solder layers have tapered portions.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: December 30, 2014
    Assignee: Toyota Motor Engineering & Manufacturing North, America, Inc.
    Inventors: Shuhei Horimoto, Ercan Mehmet Dede, Tsuyoshi Nomura
  • Publication number: 20140291696
    Abstract: Power electronics modules having solder layers with reduced thermal-stress are disclosed. In one embodiment, a power electronics module includes a power electronics device having a first surface, a second surface, a first edge, and a second edge opposite the first edge. The power electronics device has a device length measured from the first edge to the second edge. A first solder layer is adjacent to the first surface of the power electronics device, and a second solder layer is adjacent to the second surface. The first solder layer and the second solder layer have a maximum thickness T along a length that is less than the device length of the power electronics device. A first thermally conductive layer is adjacent to the first solder layer, and a second thermally conductive layer is adjacent to the second solder layer. In some embodiments, the first and second solder layers have tapered portions.
    Type: Application
    Filed: March 27, 2013
    Publication date: October 2, 2014
    Applicant: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Shuhei Horimoto, Ercan Mehmet Dede, Tsuyoshi Nomura