Patents by Inventor Shuhei Maeda
Shuhei Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240006452Abstract: A solid-state imaging element according to an aspect of the present disclosure includes a first semiconductor substrate (11), an insulating layer (46) and a second semiconductor substrate (21), a floating diffusion layer (FD) of the first semiconductor substrate (11), a transfer gate (TG) of the first semiconductor substrate (11), a first through wire (71) electrically connected to the floating diffusion layer (FD) and penetrating the insulating layer (46) and the second semiconductor substrate (21), a second through wire (72) electrically connected to the transfer gate (TG) and penetrating the insulating layer (46) and the second semiconductor substrate (21), a wiring layer (56) stacked on the second semiconductor substrate (21) and having a wiring electrically connected to the first through wire (71) or the second through wire (72), and an adjustment layer that is provided on the second semiconductor substrate (21) so as to be in contact with both or one of the first through wire (71) and the second throughType: ApplicationFiled: November 25, 2021Publication date: January 4, 2024Inventors: SHUHEI MAEDA, TAKASHI TANAKA, HIRONOBU FUKUI
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Patent number: 11843259Abstract: A wireless power feed system with high transfer efficiency of electric power is disclosed. The wireless power feed system includes a power feeding device and a power receiving device, wherein the power feeding device includes a first electromagnetic coupling coil that is connected to an AC power source via a directional coupler; a first resonant coil; a switch connected to the opposite ends of the first resonant coil; a control circuit which conducts switching on/off of the switch based on a parameter of an amplitude of a reflective wave detected by the directional coupler; and an analog-digital converter provided between the first electromagnetic coupling coil and the control circuit; and the power receiving device includes a second resonant coil; and a second electromagnetic coupling coil, and wherein the first electromagnetic coupling coil is provided between the first resonant coil and the second resonant coil.Type: GrantFiled: August 12, 2022Date of Patent: December 12, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koichiro Kamata, Misako Sato, Shuhei Maeda
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Publication number: 20230257883Abstract: There is provided a technique that includes: a reaction tube where a process chamber configured to process a substrate is formed; a heater structure including a heater heating the substrate; a cooler including a cooling valve supplying a cooling medium; an exhaust fan supplying the cooling medium to the cooler; and a cooling controller configured to: acquire a prediction model that includes information of the exhaust fan, final target temperature, and opening state of the cooling valve and estimates a predicted temperature predicting at least one selected from the group of a temperature of the heater and a temperature of the process chamber; acquire the at least one selected from the group of the temperature of the heater and the temperature of the process chamber, the opening state of the cooling valve, and the information of the exhaust fan; and regulate the opening state of the cooling valve.Type: ApplicationFiled: March 23, 2023Publication date: August 17, 2023Applicant: Kokusai Electric CorporationInventors: Hideto YAMAGUCHI, Seiya Shigematsu, Masaaki Ueno, Masashi Sugishita, Shuhei Maeda, Tetsuya Kosugi
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Publication number: 20230221700Abstract: According to one aspect of the technique of the present disclosure, there is provided a temperature control method including: (a) controlling a current heater supply power such that a predicted temperature column calculated according to a prediction model stored in advance approaches a future target temperature column, wherein the future target temperature column is updated in accordance with a current temperature, a final target temperature and one of a temperature convergence ramp rate and a designated temperature convergence time.Type: ApplicationFiled: March 8, 2023Publication date: July 13, 2023Inventors: Hideto YAMAGUCHI, Masaaki UENO, Seiya SHIGEMATSU, Masashi SUGISHITA, Shuhei MAEDA
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Publication number: 20220385108Abstract: A wireless power feed system with high transfer efficiency of electric power is disclosed. The wireless power feed system includes a power feeding device and a power receiving device, wherein the power feeding device includes a first electromagnetic coupling coil that is connected to an AC power source via a directional coupler; a first resonant coil; a switch connected to the opposite ends of the first resonant coil; a control circuit which conducts switching on/off of the switch based on a parameter of an amplitude of a reflective wave detected by the directional coupler; and an analog-digital converter provided between the first electromagnetic coupling coil and the control circuit; and the power receiving device includes a second resonant coil; and a second electromagnetic coupling coil, and wherein the first electromagnetic coupling coil is provided between the first resonant coil and the second resonant coil.Type: ApplicationFiled: August 12, 2022Publication date: December 1, 2022Inventors: Koichiro KAMATA, Misako SATO, Shuhei MAEDA
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Patent number: 11424622Abstract: A wireless power feed system with high transfer efficiency of electric power is disclosed. The wireless power feed system includes a power feeding device and a power receiving device, wherein the power feeding device includes a first electromagnetic coupling coil that is connected to an AC power source via a directional coupler; a first resonant coil; a switch connected to the opposite ends of the first resonant coil; a control circuit which conducts switching on/off of the switch based on a parameter of an amplitude of a reflective wave detected by the directional coupler; and an analog-digital converter provided between the first electromagnetic coupling coil and the control circuit; and the power receiving device includes a second resonant coil; and a second electromagnetic coupling coil, and wherein the first electromagnetic coupling coil is provided between the first resonant coil and the second resonant coil.Type: GrantFiled: February 9, 2018Date of Patent: August 23, 2022Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Koichiro Kamata, Misako Sato, Shuhei Maeda
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Patent number: 11366507Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.Type: GrantFiled: November 25, 2020Date of Patent: June 21, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shuhei Maeda, Shuhei Nagatsuka, Tatsuya Onuki, Kiyoshi Kato
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Publication number: 20210287732Abstract: A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.Type: ApplicationFiled: June 3, 2021Publication date: September 16, 2021Inventors: Tomoaki ATSUMI, Kiyoshi KATO, Shuhei MAEDA
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Patent number: 11037622Abstract: A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.Type: GrantFiled: November 12, 2018Date of Patent: June 15, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoaki Atsumi, Kiyoshi Kato, Shuhei Maeda
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Patent number: 10991477Abstract: An insulated electrical cable includes: a conductor; and an insulating layer that is laminated on an outer peripheral surface of the conductor and includes a polyimide as a main component, wherein the insulating layer includes a plurality of pores, and wherein a porosity of the insulating layer is greater than or equal to 25% by volume and less than or equal to 60% by volume.Type: GrantFiled: April 26, 2018Date of Patent: April 27, 2021Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC WINTEC, INC.Inventors: Shinya Ota, Masaaki Yamauchi, Hideaki Saito, Shuhei Maeda, Yasushi Tamura, Kengo Yoshida
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Publication number: 20210081023Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.Type: ApplicationFiled: November 25, 2020Publication date: March 18, 2021Inventors: Shuhei MAEDA, Shuhei NAGATSUKA, Tatsuya ONUKI, Kiyoshi KATO
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Patent number: 10860080Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.Type: GrantFiled: January 9, 2018Date of Patent: December 8, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shuhei Maeda, Shuhei Nagatsuka, Tatsuya Onuki, Kiyoshi Kato
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Patent number: 10832829Abstract: An insulated electric wire includes a linear conductor and one or a plurality of insulating layers formed on an outer peripheral surface of the conductor. At least one of the one or plurality of insulating layers contains a plurality of pores, outer shells are disposed on peripheries of the pores, and the outer shells are derived from shells of hollow-forming particles having a core-shell structure. A varnish for forming an insulating layer contains a resin composition forming a matrix and hollow-forming particles having a core-shell structure and dispersed in the resin composition. In the varnish, cores of the hollow-forming particles contain a thermally decomposable resin as a main component, and shells of the hollow-forming particles contain a main component having a higher thermal decomposition temperature than the thermally decomposable resin.Type: GrantFiled: October 25, 2016Date of Patent: November 10, 2020Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC WINTEC, INC.Inventors: Shinya Ota, Shuhei Maeda, Hideaki Saito, Jun Sugawara, Masaaki Yamauchi, Yasushi Tamura, Kengo Yoshida, Yudai Furuya, Yuji Hatanaka
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Publication number: 20200265887Abstract: A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.Type: ApplicationFiled: November 12, 2018Publication date: August 20, 2020Inventors: Tomoaki ATSUMI, Kiyoshi KATO, Shuhei MAEDA
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Publication number: 20200152348Abstract: An insulated electrical cable according to one aspect of the present invention is an insulated electrical cable including: a conductor; and an insulating layer that is laminated on an outer peripheral surface of the conductor and includes a polyimide as a main component, wherein the insulating layer includes a plurality of pores, and wherein a porosity of the insulating layer is greater than or equal to 25% by volume and less than or equal to 60% by volume.Type: ApplicationFiled: April 26, 2018Publication date: May 14, 2020Inventors: Shinya OTA, Masaaki YAMAUCHI, Hideaki SAITO, Shuhei MAEDA, Yasushi TAMURA, Kengo YOSHIDA
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Publication number: 20200135360Abstract: An insulated electric wire includes a linear conductor and an insulating film disposed to surround the periphery of the conductor. The insulating film includes a polyimide layer formed of a polyimide that has a molecular structure including a PMDA-ODA-type repeating unit A and a BPDA-ODA-type repeating unit B, the mole fraction [B×100/(A+B)] (% by mole) represented by the percentage of the number of moles of the repeating unit B to the total number of moles of the repeating unit A and the repeating unit B being 25% or more by mole and 95% or less by mole. The polyimide layer has a plurality of pores. The pores occupy 5% or more by volume and 80% or less by volume of the polyimide layer.Type: ApplicationFiled: June 15, 2018Publication date: April 30, 2020Inventors: Shuhei MAEDA, Masaaki YAMAUCHI, Shinya OTA, Hideaki SAITO, Yasushi TAMURA, Kengo YOSHIDA, Shigenori HOMMA
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Publication number: 20200118705Abstract: An insulated electric wire includes a conductor that has a linear shape and an insulating film that is formed to cover the periphery of the conductor. The insulating film is formed of a polyimide that has a molecular structure including a PMDA-ODA-type repeating unit A and a BPDA-ODA-type repeating unit B, the mole ratio [B/(A+B)]×100 (% by mole) of the number of moles of the repeating unit B to the total number of moles of the repeating unit A and the repeating unit B being more than 55% by mole. A first sample of the insulating film with a separation elongation of 7% has a ratio M60/M10 of 1.2 or more, or a second sample of the insulating film with a separation elongation of 40% has a ratio M30/M10 of 1.2 or more.Type: ApplicationFiled: June 15, 2018Publication date: April 16, 2020Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC WINTEC, INC.Inventors: Shuhei MAEDA, Masaaki YAMAUCHI, Tokiko UMEMOTO, Yasushi TAMURA
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Patent number: 10615849Abstract: A power receiving device and a power feeding system which are capable of performing communication and power feeding at the same time are provided. Further, a power receiving device and a power feeding system which are capable of stably performing communication during power feeding are provided. One embodiment of the present invention relates to a power receiving device which includes an antenna for communication and power feeding that receives AC power, a rectifier circuit that rectifies the received AC power including the modulation signal into DC power, a smoothing circuit that smoothes the resulting DC power, a power storage device that stores the smoothed DC power, a communication control unit that analyzes the modulation signal included in the AC power, and a transformer that is positioned between the antenna and the rectifier circuit and changes a reference potential of the AC power, and a power feeding device.Type: GrantFiled: May 1, 2017Date of Patent: April 7, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Misako Miwa, Koichiro Kamata, Shuhei Maeda
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Publication number: 20190377401Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.Type: ApplicationFiled: January 9, 2018Publication date: December 12, 2019Inventors: Shuhei MAEDA, Shuhei NAGATSUKA, Tatsuya ONUKI, Kiyoshi KATO
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Patent number: 10491183Abstract: A resonant power feeding system that can provide high power transmission efficiency between a power feeding device and a power reception device without dynamically controlling the oscillation frequency in accordance with the distance between the power feeding device and the power reception device. High power transmission efficiency between the power feeding device and the power reception device is obtained by addition of a structure for adjusting the matching condition to both the power reception device and the power feeding device. Specifically, a transmission-reception circuit and a matching circuit are provided in both the power reception device and the power feeding device, and wireless signals for adjusting the matching circuit are transmitted and received through a resonant coil. Thus, the power feeding device can efficiently supply power to the power reception device without adjusting the oscillation frequency.Type: GrantFiled: November 29, 2017Date of Patent: November 26, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koichiro Kamata, Shinya Okano, Misako Sato, Shuhei Maeda