Patents by Inventor Shuhei OKI
Shuhei OKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10319831Abstract: Technique disclosed herein can suppress performance variation among semiconductor devices to be manufactured upon manufacturing each semiconductor device by forming diffusion layer by ion implantation to semiconductor substrate after etching. A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes an emitter region, a top body region, a barrier region, a bottom body region, a drift region, a collector region, a trench, a gate insulating film, and a gate electrode. A front surface of the gate electrode is provided at a deeper position than a front surface of the semiconductor substrate. Within the gate electrode, a front surface of a first portion at a widthwise center of a trench is provided at a shallower position than a front surface of a second portion in contact with the gate insulating film.Type: GrantFiled: February 25, 2015Date of Patent: June 11, 2019Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Toru Onishi, Shuhei Oki, Tomoharu Ikeda, Rahman Md. Tasbir
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Patent number: 10074648Abstract: A method of manufacturing a semiconductor device includes: implanting charged particles into a first range and a second range in a semiconductor substrate from at least one of a first surface of the semiconductor substrate and a second surface of the semiconductor substrate located on an opposite side of the first surface so as to increase crystal defect densities in the first range and the second range; implanting n-type impurities into the first range from the first surface so as to make a region amorphous, the region being in the first range and disposed at the first surface; irradiating the first surface with first laser after the implantation of the charged particles and the implantation of the n-type impurities so as to heat the first range and the second range; and crystallizing the region which has been made amorphous in or after the irradiation of the first laser.Type: GrantFiled: September 28, 2017Date of Patent: September 11, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hiroshi Hosokawa, Shinya Iwasaki, Tsuyoshi Nishiwaki, Atsushi Imai, Shuhei Oki
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Publication number: 20180138170Abstract: A method of manufacturing a semiconductor device includes: implanting charged particles into a first range and a second range in a semiconductor substrate from at least one of a first surface of the semiconductor substrate and a second surface of the semiconductor substrate located on an opposite side of the first surface so as to increase crystal defect densities in the first range and the second range; implanting n-type impurities into the first range from the first surface so as to make a region amorphous, the region being in the first range and disposed at the first surface; irradiating the first surface with first laser after the implantation of the charged particles and the implantation of the n-type impurities so as to heat the first range and the second range; and crystallizing the region which has been made amorphous in or after the irradiation of the first laser.Type: ApplicationFiled: September 28, 2017Publication date: May 17, 2018Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hiroshi HOSOKAWA, Shinya IWASAKI, Tsuyoshi NISHIWAKI, Atsushi IMAI, Shuhei OKI
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Patent number: 9741554Abstract: A method of manufacturing a semiconductor device includes a semiconductor region forming process, a cleaning process, a surface roughness uniformizing process, and an electrode forming process. As the semiconductor region forming process, semiconductor regions are formed such that a plurality of semiconductor regions with different ion injection amounts are exposed on one principal surface of a semiconductor substrate. As the cleaning process, after the semiconductor region forming process, a cleaning using hydrofluoric acid is performed on the one principal surface of the semiconductor substrate. As the surface roughness uniformizing process, after the cleaning process, the surface roughness of the one principal surface of the semiconductor substrate is uniformized. As the electrode forming process, after the surface roughness uniformizing process, electrodes are formed on the one principal surface of the semiconductor substrate.Type: GrantFiled: December 7, 2016Date of Patent: August 22, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Satoru Kameyama, Masaki Ajioka, Shuhei Oki
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Publication number: 20170170005Abstract: A method of manufacturing a semiconductor device includes a semiconductor region forming process, a cleaning process, a surface roughness uniformizing process, and an electrode forming process. As the semiconductor region forming process, semiconductor regions are formed such that a plurality of semiconductor regions with different ion injection amounts are exposed on one principal surface of a semiconductor substrate. As the cleaning process, after the semiconductor region forming process, a cleaning using hydrofluoric acid is performed on the one principal surface of the semiconductor substrate. As the surface roughness uniformizing process, after the cleaning process, the surface roughness of the one principal surface of the semiconductor substrate is uniformized. As the electrode forming process, after the surface roughness uniformizing process, electrodes are formed on the one principal surface of the semiconductor substrate.Type: ApplicationFiled: December 7, 2016Publication date: June 15, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Satoru KAMEYAMA, Masaki AJIOKA, Shuhei OKI
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Patent number: 9633997Abstract: A semiconductor device, in which, in a density distribution of first conductivity type impurities in the first conductivity type region measured along a thickness direction of the semiconductor substrate, a local maximum value N1, a local minimum value N2, a local maximum value N3, and a density N4 are formed in this order from front surface side, a relationship of N1>N3>N2>N4 is satisfied, a relationship of N3/10>N2 is satisfied, and a distance “a” from the surface to the depth having the local maximum value N1 is larger than twice a distance “b” from the depth having the local maximum value N1 to the depth having the local minimum N2.Type: GrantFiled: September 8, 2014Date of Patent: April 25, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Satoru Kameyama, Shinya Iwasaki, Yuki Horiuchi, Shuhei Oki
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Publication number: 20170033195Abstract: Technique disclosed herein can suppress performance variation among semiconductor devices to be manufactured upon manufacturing each semiconductor device by forming diffusion layer by ion implantation to semiconductor substrate after etching. A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes an emitter region, a top body region, a barrier region, a bottom body region, a drift region, a collector region, a trench, a gate insulating film, and a gate electrode. A front surface of the gate electrode is provided at a deeper position than a front surface of the semiconductor substrate. Within the gate electrode, a front surface of a first portion at a widthwise center of a trench is provided at a shallower position than a front surface of a second portion in contact with the gate insulating film.Type: ApplicationFiled: February 25, 2015Publication date: February 2, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Toru ONISHI, Shuhei OKI, Tomoharu IKEDA, Rahman MD. TASBIR
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Publication number: 20170012039Abstract: A semiconductor device, in which, in a density distribution of first conductivity type impurities in the first conductivity type region measured along a thickness direction of the semiconductor substrate, a local maximum value N1, a local minimum value N2, a local maximum value N3, and a density N4 are formed in this order from front surface side, a relationship of N1>N3>N2>N4 is satisfied, a relationship of N3/10>N2 is satisfied, and a distance “a” from the surface to the depth having the local maximum value N1 is larger than twice a distance “b” from the depth having the local maximum value N1 to the depth having the local minimum N2.Type: ApplicationFiled: September 8, 2014Publication date: January 12, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Satoru KAMEYAMA, Shinya IWASAKI, Yuki HORIUCHI, Shuhei OKI
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Patent number: 9530859Abstract: A manufacturing method for a semiconductor device including a drift layer; a body layer contacting a front surface of the drift layer; an emitter layer provided on a portion of a front surface of the body layer and exposed on the front surface of the substrate; a buffer layer contacting a back surface of the drift layer; a collector layer contacting a back surface of the buffer layer and exposed on a back surface of the substrate; and a gate electrode facing, via an insulator, the body layer in an area where the body layer separates the emitter layer from the drift layer, includes preparing a wafer that includes a first layer, and a second layer layered on a back surface of the first layer and having a higher polycrystalline silicon concentration than the first layer, and forming the buffer layer by implanting and diffusing ions in the second layer.Type: GrantFiled: November 21, 2013Date of Patent: December 27, 2016Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shuhei Oki, Tsuyoshi Nishiwaki
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Patent number: 9490127Abstract: A method includes: forming a front surface structure of a semiconductor element on a front surface side of a semiconductor substrate; forming crystal defects in the semiconductor substrate by implanting charged particles into the semiconductor substrate; subjecting the semiconductor substrate to a heat treatment after having formed the crystal defects; attaching a supporting plate on the front surface side of the semiconductor substrate after the heat treatment; thinning the semiconductor substrate by grinding a back surface side of the semiconductor substrate to which the supporting plate has been attached; and forming a back surface structure of the semiconductor element on a back surface of the thinned semiconductor substrate.Type: GrantFiled: January 19, 2015Date of Patent: November 8, 2016Assignee: Toyota Jidosha Kabushiki KaishaInventors: Kunihito Kato, Shuhei Oki, Takahiro Ito
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Patent number: 9437719Abstract: A technology for reducing contact resistance between a semiconductor substrate and an electrode is provided. A provided method for manufacturing a semiconductor device includes: forming an oxide film 62 on a surface 12b of a semiconductor substrate 12 by bringing the surface 12b into contact with ammonia-hydrogen peroxide water mixture; forming a groove 60 on the surface 12b by irradiating light to heat the surface 12b covered with the oxide film 62; removing the oxide film 62 to expose the surface 12b; and forming an electrode 16 on the exposed surface 12b.Type: GrantFiled: February 12, 2015Date of Patent: September 6, 2016Assignee: Toyota Jidosha Kabushiki KaishaInventors: Shuhei Oki, Masaru Senoo
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Publication number: 20150249084Abstract: A technology for reducing contact resistance between a semiconductor substrate and an electrode is provided. A provided method for manufacturing a semiconductor device includes: forming an oxide film 62 on a surface 12b of a semiconductor substrate 12 by bringing the surface 12b into contact with ammonia-hydrogen peroxide water mixture; forming a groove 60 on the surface 12b by irradiating light to heat the surface 12b covered with the oxide film 62; removing the oxide film 62 to expose the surface 12b; and forming an electrode 16 on the exposed surface 12b.Type: ApplicationFiled: February 12, 2015Publication date: September 3, 2015Inventors: Shuhei Oki, Masaru Senoo
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Publication number: 20150206758Abstract: A method includes: forming a front surface structure of a semiconductor element on a front surface side of a semiconductor substrate; forming crystal defects in the semiconductor substrate by implanting charged particles into the semiconductor substrate; subjecting the semiconductor substrate to a heat treatment after having formed the crystal defects; attaching a supporting plate on the front surface side of the semiconductor substrate after the heat treatment; thinning the semiconductor substrate by grinding a back surface side of the semiconductor substrate to which the supporting plate has been attached; and forming a back surface structure of the semiconductor element on a back surface of the thinned semiconductor substrate.Type: ApplicationFiled: January 19, 2015Publication date: July 23, 2015Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Kunihito Kato, Shuhei Oki, Takahiro Ito
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Publication number: 20140145239Abstract: A manufacturing method for a semiconductor device including a drift layer; a body layer contacting a front surface of the drift layer; an emitter layer provided on a portion of a front surface of the body layer and exposed on the front surface of the substrate; a buffer layer contacting a back surface of the drift layer; a collector layer contacting a back surface of the buffer layer and exposed on a back surface of the substrate; and a gate electrode facing, via an insulator, the body layer in an area where the body layer separates the emitter layer from the drift layer, includes preparing a wafer that includes a first layer, and a second layer layered on a back surface of the first layer and having a higher polycrystalline silicon concentration than the first layer, and forming the buffer layer by implanting and diffusing ions in the second layer.Type: ApplicationFiled: November 21, 2013Publication date: May 29, 2014Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shuhei OKI, Tsuyoshi NISHIWAKI