Abstract: Provided is a test method comprising: preparing a plurality of groups for setting, each of which has a plurality of semiconductor devices for setting, and assigning an inspection voltage to each of the respective plurality of groups for setting; performing first testing by applying the assigned inspection voltage to the semiconductor devices for setting, and testing, at a first temperature, the plurality of semiconductor devices for setting included in each of the plurality of groups for setting; performing second testing by testing, at a second temperature different from the first temperature, a semiconductor device for setting having been determined as being non-defective and by detecting a breakdown voltage at which the semiconductor device for setting is broken; acquiring a relationship between the inspection voltage and the breakdown voltage; and setting an applied voltage used when testing a semiconductor device under test at the first temperature, based on the acquired relationship.

Abstract: A method of manufacturing a semiconductor device that includes a semiconductor layer of a first conductivity type, and a parallel pn layer formed on the semiconductor layer, the pn layer having first semiconductor regions of the first conductivity type and second semiconductor regions of a second conductivity type, the first and second regions being alternately arranged parallel to a surface of the semiconductor layer. In one embodiment, the method includes repeatedly performing the following steps to stack the epitaxial growth layers on the semiconductor layer to form the pn layer: forming an epitaxial growth layer of the first conductivity type or non-doped, the epitaxial growth layer having an impurity concentration lower than that of the semiconductor layer, ion implanting a first-conductivity-type impurity into the epitaxial growth layer, selectively ion implanting a second-conductivity-type impurity into the epitaxial growth layer and ion implanting a group 18 element into the epitaxial growth layer.

Abstract: A method of manufacturing a semiconductor device that includes a semiconductor layer of a first conductivity type, and a parallel pn layer formed on the semiconductor layer, the pn layer having first semiconductor regions of the first conductivity type and second semiconductor regions of a second conductivity type, the first and second regions being alternately arranged parallel to a surface of the semiconductor layer. In one embodiment, the method includes repeatedly performing the following steps to stack the epitaxial growth layers on the semiconductor layer to form the pn layer: forming an epitaxial growth layer of the first conductivity type or non-doped, the epitaxial growth layer having an impurity concentration lower than that of the semiconductor layer, ion implanting a first-conductivity-type impurity into the epitaxial growth layer, selectively ion implanting a second-conductivity-type impurity into the epitaxial growth layer and ion implanting a group 18 element into the epitaxial growth layer.

Abstract: A semiconductor device, including a semiconductor layer of a first conductivity type, and a parallel pn layer formed on a surface of the semiconductor layer. The parallel pn layer includes a plurality of first semiconductor regions of the first conductivity type, and a plurality of second semiconductor regions of a second conductivity type. The first and second semiconductor regions are alternatingly arranged in a direction parallel to the surface of the semiconductor layer. Each second semiconductor region has at least one first region that is a region having a group 18 element introduced therein.

Abstract: A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.

Abstract: A semiconductor device, including a semiconductor layer of a first conductivity type, and a parallel pn layer formed on a surface of the semiconductor layer. The parallel pn layer includes a plurality of first semiconductor regions of the first conductivity type, and a plurality of second semiconductor regions of a second conductivity type. The first and second semiconductor regions are alternatingly arranged in a direction parallel to the surface of the semiconductor layer. Each second semiconductor region has at least one first region that is a region having a group 18 element introduced therein.

Abstract: A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.

Abstract: A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.

Abstract: A MOS semiconductor device has a MOS structure, including a p? region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n+-type source region and a surface layer of an n? layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.

Abstract: A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.

Abstract: A MOS semiconductor device has a MOS structure, including a p? region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n+-type source region and a surface layer of an n? layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.

Abstract: A method of manufacturing a MOS-type semiconductor device capable of increasing the thickness of a gate oxide film and obtaining high gate withstanding power and reduced switching loss without increasing a gate threshold voltage Vth is provided. A p-type well region is selectively formed on one principle surface of a semiconductor substrate having an n-type low impurity concentration layer by using an oxide film as a mask. Subsequently, a resist mask is formed on the surface of the p-type well region so as to be separated from the oxide film mask, and an n+-type source region is selectively formed from the separation portion. Subsequently, the oxide film mask is removed. Then, an oxide film is formed on the surface of the p-type well region, and the oxide film is removed. Subsequently, a gate electrode coated with a gate oxide film is formed on the surface of the semiconductor substrate.

Abstract: A MOS semiconductor device has a MOS structure, including a p? region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n+-type source region and a surface layer of an n? layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.

Abstract: A method of manufacturing a MOS-type semiconductor device capable of increasing the thickness of a gate oxide film and obtaining high gate withstanding power and reduced switching loss without increasing a gate threshold voltage Vth is provided. A p-type well region is selectively formed on one principle surface of a semiconductor substrate having an n-type low impurity concentration layer by using an oxide film as a mask. Subsequently, a resist mask is formed on the surface of the p-type well region so as to be separated from the oxide film mask, and an n+-type source region is selectively formed from the separation portion. Subsequently, the oxide film mask is removed. Then, an oxide film is formed on the surface of the p-type well region, and the oxide film is removed. Subsequently, a gate electrode coated with a gate oxide film is formed on the surface of the semiconductor substrate.

Abstract: A MOS semiconductor device has a MOS structure, including a p? region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n+-type source region and a surface layer of an n? layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.