Patents by Inventor Shuhua Xiang
Shuhua Xiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9165059Abstract: Systems, methods, and other embodiments associated with flexible bit field search are described. According to one embodiment, an apparatus includes a filter configured to receive data packets and a descriptor. The descriptor includes a header and at least one filter descriptor rule. The header identifies a filtering mode. The at least one filter descriptor rule includes instructions that identify a filtering operation in the filtering mode. The filter is also configured to filter the data packets based, at least in part, on the filtering operation identified in the at least one filter descriptor rule.Type: GrantFiled: February 3, 2014Date of Patent: October 20, 2015Assignee: MARVELL INTERNATIONAL LTD.Inventors: Shuhua Xiang, Venkata Narayana Pinnamaraju Durga
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Patent number: 9055296Abstract: Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.Type: GrantFiled: June 27, 2013Date of Patent: June 9, 2015Assignee: Marvell World Trade Ltd.Inventors: Shuhua Xiang, Li Sha, Ching-Han Tsai
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Patent number: 8878870Abstract: Embodiments of the present invention provide graphic processing techniques and configurations including an apparatus comprising a storage medium having stored therein a table comprising information about respective positions and sizes of a number of rectangular blocks, the rectangular blocks to substantially form at least one plane having an arbitrary shape object, and at least one overlay engine operatively coupled with the table and associated with the at least one plane to request the information about the respective positions and the sizes of the number of rectangular blocks to provide graphics overlay of the arbitrary shape object. Other embodiments may be described and/or claimed.Type: GrantFiled: July 31, 2009Date of Patent: November 4, 2014Assignee: Marvell International Ltd.Inventors: Satish Kumar Vutukuri, Haohong Wang, Li Sha, Tao Xie, Ching-Han Tsai, Tzun-Wei Lee, Leung Chung Lai, Shuhua Xiang
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Patent number: 8645400Abstract: A method and apparatus uses a section filter to perform a filtering operation, such as a match, do not match, within range, or without range filtering operation, on bitstream data in accordance with a rule. The filtering operation may begin at any bit location in the bitstream data and end at any location in the bitstream data. The result of the filtering operation is compared to a value determined by the rule, or if further rules are to be employed, the result is transmitted to a further section filter which performs a further filtering operation on the bitstream data. As many section filters may be linked in this way as the number of rules to be employed. When the section filter corresponding to the last rule to be employed has performed its filtering operation, all results are compared to values determined by the rules employed to determine which data to extract from the bitstream data.Type: GrantFiled: July 30, 2009Date of Patent: February 4, 2014Assignee: Marvell International Ltd.Inventors: Shuhua Xiang, Venkata Narayana Pinnamaraju Durga
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Patent number: 8587609Abstract: Embodiments of the present invention provide methods and associated architecture of accuracy adaptive and scalable vector graphics rendering including rendering a graphic comprising a plurality of line segments by processing each of the plurality of line segments in a first pass, and processing each of a plurality of pixels through which the plurality of line segments pass in a second pass, automatically detecting one or more rendering errors of the graphic, and correcting the one or more rendering errors. Other embodiments may be described and/or claimed.Type: GrantFiled: July 28, 2009Date of Patent: November 19, 2013Assignee: Marvell International Ltd.Inventors: Haohong Wang, Yunsen Chin, Li Sha, Shuhua Xiang
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Publication number: 20130287119Abstract: Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.Type: ApplicationFiled: June 27, 2013Publication date: October 31, 2013Inventors: Shuhua XIANG, Li SHA, Ching-Han TSAI
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Patent number: 8477146Abstract: Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.Type: GrantFiled: July 29, 2009Date of Patent: July 2, 2013Assignee: Marvell World Trade Ltd.Inventors: Shuhua Xiang, Li Sha, Ching-Han Tsai
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Publication number: 20100026697Abstract: Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.Type: ApplicationFiled: July 29, 2009Publication date: February 4, 2010Inventors: Shuhua XIANG, Li SHA, Ching-Han TSAI
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Patent number: 7516259Abstract: The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.Type: GrantFiled: May 19, 2008Date of Patent: April 7, 2009Assignee: Micronas USA, Inc.Inventors: Enoch Lee, Li Sha, Shuhua Xiang
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Publication number: 20080313357Abstract: A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on selecting a combination of access and operation modes. In another embodiment, a video processing system capable of selectably enabling a plurality of data transfer modes along one or more channels is described.Type: ApplicationFiled: August 20, 2008Publication date: December 18, 2008Applicant: MICRONAS USA, INC.Inventors: Xu Wang, Shuhua Xiang, Sha Li
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Patent number: 7432988Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.Type: GrantFiled: February 26, 2007Date of Patent: October 7, 2008Assignee: Micronas USA, Inc.Inventors: Shuhua Xiang, Hongjun Yuan, Li Sha
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Patent number: 7430621Abstract: A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on selecting a combination of access and operation modes. In another embodiment, a video processing system capable of selectably enabling a plurality of data transfer modes along one or more channels is described.Type: GrantFiled: December 16, 2005Date of Patent: September 30, 2008Assignee: Micronas USA, Inc.Inventors: Xu Wang, Shuhua Xiang, Sha Li
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Publication number: 20080222332Abstract: The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.Type: ApplicationFiled: May 19, 2008Publication date: September 11, 2008Applicant: MICRONAS USA, INC.Inventors: Enoch Y. LEE, Li SHA, Shuhua XIANG
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Patent number: 7380036Abstract: The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.Type: GrantFiled: October 25, 2005Date of Patent: May 27, 2008Assignee: Micronas USA, Inc.Inventors: Enoch Y. Lee, Li Sha, Shuhua Xiang
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Patent number: 7359006Abstract: A system and method embed an audio signature in a video frame. An audio signature is generated from one bit a buffer input data. Two registers store an audio signature and reference count. According to an embodiment, the audio signature is generated left/right (L/R) interleaved with the left channel data in the most significant bit (MSB).Type: GrantFiled: May 20, 2004Date of Patent: April 15, 2008Assignee: Micronas USA, Inc.Inventors: Shuhua Xiang, Hongjun Yuan
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Publication number: 20070153133Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.Type: ApplicationFiled: February 26, 2007Publication date: July 5, 2007Inventors: Shuhua Xiang, Hongjun Yuan, Sha Li
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Patent number: 7219173Abstract: A method, apparatus, computer medium, and other embodiments for synchronizing control of one or more devices at predetermined times are described. A host scheduler loads a to-do list of predetermined events and corresponding time-tags into memory and broadcasts scheduled events to the devices to cause activation of the events on intended devices.Type: GrantFiled: November 2, 2001Date of Patent: May 15, 2007Assignee: Micronas USA, Inc.Inventors: Li Sha, Shuhua Xiang, Wang Xu
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Patent number: 7184101Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.Type: GrantFiled: July 25, 2002Date of Patent: February 27, 2007Assignee: Micronas USA, Inc.Inventors: Shuhua Xiang, Hongjun Yuan, Sha Li
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Patent number: 7142251Abstract: A video input processor is provided to process different input video format, including RGB, RGB Bayer, YUV 4:2:2 interlaced and progressive video data. The video input processor also uses an advanced algorithm to efficiently convert video data in RGB color space to YUV color space. The video input processor further enables multi-functions such as video image scaling, video image filtering before the video data are output for further video compression.Type: GrantFiled: July 31, 2002Date of Patent: November 28, 2006Assignee: Micronas USA, Inc.Inventors: Li Sha, Shuhua Xiang, Yaojun Luo, He Ouyang
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Patent number: 7085320Abstract: A video compression scheme enables the user to select one of many video compression formats, including the widely-used standard video formats such as MPEG-1, MPEG-2, MPEG-4 and H.263. In one embodiment, the scheme is implemented as a hardware-software combination, with the hardware portion, preferably implemented as an ASIC chip, performing the core compression and the software portion dealing with the detailed formatting. In another embodiment, a 32-bit aligned transitional data format is used.Type: GrantFiled: September 14, 2001Date of Patent: August 1, 2006Assignee: WIS Technologies, Inc.Inventors: He Ouyang, Li Sha, Shuhua Xiang, Yaojun Luo, Weimin Zeng, Jun Ding