Patents by Inventor Shui-Hung Chen

Shui-Hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12152697
    Abstract: A control valve includes a valve body and a valve gate. The valve gate is movably located inside the inner space. The control valve has a lower flow rate limit which is greater than zero. That is, the lower flow rate limit has no necessary to be zero, thus it is acceptable to have a cylindrical valve gate but not a spherical valve gate, and a diameter of the cylindrical valve gate is be smaller than a caliber of an opening of the valve body. Therefore, the valve gate can be directly installed into the valve body via the opening, which allows the valve body to be made of a single piece so as to simplify the processes of manufacturing and assembly.
    Type: Grant
    Filed: June 13, 2023
    Date of Patent: November 26, 2024
    Assignee: COOLER MASTER CO., LTD.
    Inventors: Shui-Fa Tsai, Sy-Chi Kuo, Hsin-Hung Chen
  • Patent number: 8018000
    Abstract: Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be a higher-doped region within which the drain/source lies. The junction between the higher doping of this island region and the surrounding substrates operates to limit the amount of current that passes through the drain/source. Additionally, oxide features may be used to create an island surrounding the drain/source contact. Again, this isolating effect makes the amount of current passing through the device more uniform, which protects the device from damage due to an ESD event.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: September 13, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shui-Hung Chen, Jian-Hsing Lee, Yung-Tien Tsai, Anthony Oates
  • Patent number: 7826193
    Abstract: The present invention relates to an electrostatic discharge (ESD) protection scheme and particularly to a string contact structure for an improved ESD performance. In an embodiment, the invention provides a method for forming an ESD protection circuit for protecting an internal circuit from damage due to an ESD voltage appearing on a pad coupled to a clamp device including a first terminal and a second terminal. The method includes forming a string contact along the first terminal and the second terminal of the clamp device. The method further includes forming one or more conductive layers on the string contact to couple the first terminal and the second terminal of the clamp device to the pad and a ground pad.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: November 2, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Dah-Jyh Perng, Shui-Hung Chen, Jian-Hsing Lee, Huang Yung-Sheng
  • Publication number: 20090179270
    Abstract: Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be a higher-doped region within which the drain/source lies. The junction between the higher doping of this island region and the surrounding substrates operates to limit the amount of current that passes through the drain/source. Additionally, oxide features may be used to create an island surrounding the drain/source contact. Again, this isolating effect makes the amount of current passing through the device more uniform, which protects the device from damage due to an ESD event.
    Type: Application
    Filed: March 11, 2008
    Publication date: July 16, 2009
    Inventors: Shui-Hung Chen, Jian-Hsing Lee, Yung-Tien Tsai, Anthony Oates
  • Patent number: 7508639
    Abstract: Input/output devices with robustness of ESD protection are provided. An input/output device comprises an input/output pad, a first NMOS transistor, a second NMOS transistor and an ESD detector. The first NMOS transistor comprises a first drain, a first source and a first gate, wherein the first source and the first gate are coupled to a first ground power rail, and the first drain to the input/output pad. The second NMOS transistor comprises a second drain, a second source and a second gate, wherein the second source is coupled to the first ground power rail, the second drain to the input/output pad, and the second gate to a first pre-driver. When an ESD event is detected, the ESD detector makes the first pre-driver couple the second gate to the first ground power rail, thereby the first and second transistors evenly discharge ESD current.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: March 24, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsun Wu, Jian-Hsing Lee, Shui-Hung Chen
  • Patent number: 7462885
    Abstract: An electrostatic discharge-protected MOS structure is disclosed. An electrostatic discharge-protected MOS structure includes a semiconductor substrate of a first type, a first well of the first type formed in the semiconductor substrate, and a second well of a second type disposed adjacent to the first well. The MOS structure further includes a source region, a drain region, and an oxide layer and a polysilicon layer for forming a gate electrode of the MOS structure. In addition, the MOS structure includes a parasitic SCR comprising at least a parasitic NPN bipolar transistor and a buried layer of the second type interposed between the second well and the semiconductor substrate. The buried layer functions to lower a resistance of the semiconductor substrate during an ESD event so that ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: December 9, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co.
    Inventors: Shui-Hung Chen, Jian-Hsing Lee, Yi-Hsun Wu, D. J. Perng, Anthony Oates
  • Publication number: 20080128818
    Abstract: An electrostatic discharge-protected MOS structure is disclosed. An electrostatic discharge-protected MOS structure includes a semiconductor substrate of a first type, a first well of the first type formed in the semiconductor substrate, and a second well of a second type disposed adjacent to the first well. The MOS structure further includes a source region, a drain region, and an oxide layer and a polysilicon layer for forming a gate electrode of the MOS structure. In addition, the MOS structure includes a parasitic SCR comprising at least a parasitic NPN bipolar transistor and a buried layer of the second type interposed between the second well and the semiconductor substrate. The buried layer functions to lower a resistance of the semiconductor substrate during an ESD event so that ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure.
    Type: Application
    Filed: November 30, 2006
    Publication date: June 5, 2008
    Inventors: Shui-Hung Chen, Jian-Hsing Lee, Yi-Hsun Wu, D. J. Perng, Anthony Oates
  • Publication number: 20080093672
    Abstract: The present invention relates to an electrostatic discharge (ESD) protection scheme and particularly to a string contact structure for an improved ESD performance. In an embodiment, the invention provides a method for forming an ESD protection circuit for protecting an internal circuit from damage due to an ESD voltage appearing on a pad coupled to a clamp device including a first terminal and a second terminal. The method includes forming a string contact along the first terminal and the second terminal of the clamp device. The method further includes forming one or more conductive layers on the string contact to couple the first terminal and the second terminal of the clamp device to the pad and a ground pad.
    Type: Application
    Filed: October 23, 2006
    Publication date: April 24, 2008
    Inventors: D. J. Perng, Shui-Hung Chen, Jian-Hsing Lee, Huang Yung-Sheng
  • Patent number: 7256975
    Abstract: An electrostatic discharge (ESD) protection circuit and method thereof are presented. In some embodiments, a high voltage tolerant input/output circuit comprises an ESD detection circuit, a first first-type transistor, a first second-type transistor, and a second second-type transistor. The first first-type transistor and the first second-type transistor are coupled to a pad. The ESD detection circuit determines whether ESD occurs at the pad and, if so, couples the gates of the first and second second-type transistors to the second power rail.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: August 14, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsun Wu, Jian-Hsing Lee, Shui-Hung Chen
  • Patent number: 7247543
    Abstract: A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: July 24, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiaw-Ren Shih, Jian-Hsing Lee, Shui-Hung Chen
  • Patent number: 7122857
    Abstract: A method is provided for forming a highly dense stacked gate flash memory cell with a structure having multi floating gates that can assume 4 states and, therefore, store 2 bits at the same time. This is accomplished by providing a semiconductor substrate having gate oxide formed thereon, and shallow trench isolation and a p-well formed therein. A layer of nitride is next formed over the substrate and an opening formed therein. Polysilicon floating gate spacers are formed in the opening. A dielectric layer is then formed over the floating gates followed by the forming of a control gate. The adjacent nitride layer is then removed leaving a multi-level structure comprising a control gate therebetween multi floating gates with the intervening dielectric layer.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: October 17, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chrong Jung Lin, Shui-Hung Chen, Hsin-Ming Chen
  • Patent number: 7078772
    Abstract: This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: July 18, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsu Wu, Jian-Hsing Lee, Shui-Hung Chen
  • Publication number: 20060114629
    Abstract: Input/output devices with robustness of ESD protection are provided. An input/output device comprises an input/output pad, a first NMOS transistor, a second NMOS transistor and an ESD detector. The first NMOS transistor comprises a first drain, a first source and a first gate, wherein the first source and the first gate are coupled to a first ground power rail, and the first drain to the input/output pad. The second NMOS transistor comprises a second drain, a second source and a second gate, wherein the second source is coupled to the first ground power rail, the second drain to the input/output pad, and the second gate to a first pre-driver. When an ESD event is detected, the ESD detector makes the first pre-driver couple the second gate to the first ground power rail, thereby the first and second transistors evenly discharge ESD current.
    Type: Application
    Filed: December 19, 2005
    Publication date: June 1, 2006
    Inventors: Yi-Hsun Wu, Jian-Hsing Lee, Shui-Hung Chen
  • Patent number: 6992361
    Abstract: A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: January 31, 2006
    Inventors: Jiaw-Ren Shin, Jian-Hsing Lee, Shui-Hung Chen
  • Publication number: 20050274990
    Abstract: This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.
    Type: Application
    Filed: June 8, 2004
    Publication date: December 15, 2005
    Inventors: Yi-Hsu Wu, Jian-Hsing Lee, Shui-Hung Chen
  • Publication number: 20050275987
    Abstract: An electrostatic discharge (ESD) protection circuit and method thereof are presented. In some embodiments, a high voltage tolerant input/output circuit comprises an ESD detection circuit, a first first-type transistor, a first second-type transistor, and a second second-type transistor. The first first-type transistor and the first second-type transistor are coupled to a pad. The ESD detection circuit determines whether ESD occurs at the pad and, if so, couples the gates of the first and second second-type transistors to the second power rail.
    Type: Application
    Filed: June 14, 2004
    Publication date: December 15, 2005
    Inventors: Yi-Hsun Wu, Jian-Hsing Lee, Shui-Hung Chen
  • Patent number: 6937457
    Abstract: A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: August 30, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiaw-Ren Shih, Jian-Hsing Lee, Shui-Hung Chen
  • Publication number: 20050176195
    Abstract: A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.
    Type: Application
    Filed: March 4, 2005
    Publication date: August 11, 2005
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiaw-Ren Shih, Jian-Hsing Lee, Shui-Hung Chen
  • Publication number: 20050158938
    Abstract: A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Jiaw-Ren Shin, Jian-Hsing Lee, Shui-Hung Chen
  • Patent number: 6888248
    Abstract: A multi-level metal interconnect structure and method for forming the same for improving a resistance of CMOS transistors to electrostatic discharge (ESD) transient events is disclosed. A semiconductor device including at least one NMOS transistor electrically connected along at least one circuit pathway to an input/output signal source and a reference voltage potential; and, electrically connecting at least the input/output signal source to the at least one NMOS transistor with a metal interconnect line extended in length by compacting at least a portion of the metal interconnect line length portion into a serpentine shape within a predetermined volume of the semiconductor device.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: May 3, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Shui-Hung Chen, Jian-Hsing Lee, Jiaw-Ren Shih