Patents by Inventor Shui Hun Yi Chen

Shui Hun Yi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for four direction low capacitance ESD protection
    Patent number: 7179691
    Abstract: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Vss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device and its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: February 20, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hsing Lee, Shui Hun Yi Chen