Patents by Inventor Shuichi Chiba

Shuichi Chiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240116914
    Abstract: It is an object of the present invention to provide a compound for a capping layer that has a high refractive index and a low extinction coefficient in a range of 450 nm to 750 nm to improve the light extraction efficiency of an organic EL element. The present invention has focused on the fact that compounds having a benzene skeleton at the center thereof are excellent in stability and also durability in the form of a thin film, and that the refractive index thereof can be improved by modifying the molecular structure, and thus, molecules have been designed. Provided is a compound represented by a general formula (1), and an organic EL element with excellent luminance efficiency is obtained by using that compound as a constituent material of a capping layer.
    Type: Application
    Filed: February 10, 2022
    Publication date: April 11, 2024
    Applicant: HODOGAYA CHEMICAL CO., LTD.
    Inventors: Eriko CHIBA, Takeshi YAMAMOTO, Kouki KASE, Yuta HIRAYAMA, Shuichi HAYASHI
  • Publication number: 20240005603
    Abstract: An information processing apparatus generates heart shape data indicating a three-dimensional shape including an internal structure of a heart of a subject based on echo image data indicating a cross-sectional image of the heart. The information processing apparatus then generates thorax shape data indicating a three-dimensional shape of a thorax of the subject based on X-ray image data indicating an X-ray image of the thorax of the subject. The information processing apparatus then decides, based on an image of the heart appearing in the X-ray image, a position and an orientation of the three-dimensional shape of the heart indicated by the heart shape data within the three-dimensional shape of the thorax indicated by the thorax shape data.
    Type: Application
    Filed: June 21, 2023
    Publication date: January 4, 2024
    Applicants: Fujitsu Limited, Japan Medical Device Corporation, UT-Heart Inc.
    Inventors: Jinse Shimo, Kazuo Minami, Shuichi Chiba, Yoshihiko Tokumaru, Takafumi Okano, Seiryo Sugiura, Jun-ichi Okada, Toshiaki Hisada, Takumi Washio, Masahiro Watanabe, Yasutomo Shimizu
  • Patent number: 11231917
    Abstract: An information processing apparatus includes a memory; and a processor coupled to the memory and the processor configured to when source code includes an instruction for storing units of data in an area of an N-dimensional variable-length array (N being an integer and a value of N being equal to or greater than 2), generate object code in the memory to cause the units of data to be stored in an area of an N-dimensional fixed-length array instead of the area of the N-dimensional variable-length array, and when the source code includes an instruction for successively accessing the unit of data stored in the area of the N-dimensional variable-length array, generate the object code in the memory to cause the units of data stored in the area of the N-dimensional fixed-length array to be stored contiguously in an area of a one-dimensional fixed-length array.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: January 25, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Tomoko Nikko, Shuichi Chiba
  • Patent number: 10831235
    Abstract: Provided is an electronic device that suppresses an increase in internal pressure while suppressing entry of a foreign material. An electronic module according to the present embodiment has an electronic device, a substrate, a frame, and a cover, a hole portion having a first opening in a first main surface and a second opening in a second main surface and communicating the internal space and the external space, and a component is disposed to face the second opening.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: November 10, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yu Katase, Tadashi Kosaka, Koichi Shimizu, Shuichi Chiba, Kazuya Notsu, Hisatane Komori, Satoru Hamasaki, Ikuto Kimura
  • Patent number: 10735673
    Abstract: According to the disclosure, a relationship of Tgp>Tgf, ?f1<?PCB1, and (Tgp?To)×?PCB1<(Tgf?To)×?f1+(Tgp?Tgf)×?f2 or a relationship of Tgp<Tgf, ?PCB1<?f1, and (Tgf?To)×?f1<(Tgp?To)×?PCB1+(Tgf?Tgp)×?PCB2 is satisfied, where linear expansion coefficients in an in-plane direction of the substrate at a temperature below a glass transition temperature Tgp of the substrate and at a temperature above the glass transition temperature Tgp of the substrate are denoted as ?PCB1 and ?PCB2, respectively, linear expansion coefficient of the frame at a temperature below a glass transition temperature Tgf of the frame and at a temperature above the glass transition temperature Tgf of the frame are denoted as ?f1 and ?f2, respectively, and a room temperature is denoted as To.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: August 4, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koichi Shimizu, Tadashi Kosaka, Shuichi Chiba, Kazuya Notsu, Hisatane Komori, Satoru Hamasaki, Yu Katase
  • Publication number: 20190391795
    Abstract: An information processing apparatus includes a memory; and a processor coupled to the memory and the processor configured to when source code includes an instruction for storing units of data in an area of an N-dimensional variable-length array (N being an integer and a value of N being equal to or greater than 2), generate object code in the memory to cause the units of data to be stored in an area of an N-dimensional fixed-length array instead of the area of the N-dimensional variable-length array, and when the source code includes an instruction for successively accessing the unit of data stored in the area of the N-dimensional variable-length array, generate the object code in the memory to cause the units of data stored in the area of the N-dimensional fixed-length array to be stored contiguously in an area of a one-dimensional fixed-length array.
    Type: Application
    Filed: May 24, 2019
    Publication date: December 26, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Tomoko Nikko, Shuichi Chiba
  • Publication number: 20190335119
    Abstract: According to the disclosure, a relationship of Tgp>Tgf, ?f1<?PCB1, and (Tgp-To) ×?PCB1<(Tgf-To)×?f1+(Tgp-Tgf)×?f2 or a relationship of Tgp<Tgf, ?PCB1<?f1, and (Tgf-To)×?f1<(Tgp-To)×?PCB1+(Tgf-Tgp)×?PCB2 is satisfied, where linear expansion coefficients in an in-plane direction of the substrate at a temperature below a glass transition temperature Tgp of the substrate and at a temperature above the glass transition temperature Tgp of the substrate are denoted as ?PCB1 and ?PCB2, respectively, linear expansion coefficient of the frame at a temperature below a glass transition temperature Tgf of the frame and at a temperature above the glass transition temperature Tgf of the frame are denoted as ?f1 and ?f2, respectively, and a room temperature is denoted as To.
    Type: Application
    Filed: April 19, 2019
    Publication date: October 31, 2019
    Inventors: Koichi Shimizu, Tadashi Kosaka, Shuichi Chiba, Kazuya Notsu, Hisatane Komori, Satoru Hamasaki, Yu Katase
  • Publication number: 20190294213
    Abstract: Provided is an electronic device that suppresses an increase in internal pressure while suppressing entry of a foreign material. An electronic module according to the present embodiment has an electronic device, a substrate, a frame, and a cover, a hole portion having a first opening in a first main surface and a second opening in a second main surface and communicating the internal space and the external space, and a component is disposed to face the second opening.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 26, 2019
    Inventors: Yu Katase, Tadashi Kosaka, Koichi Shimizu, Shuichi Chiba, Kazuya Notsu, Hisatane Komori, Satoru Hamasaki, Ikuto Kimura
  • Patent number: 10319867
    Abstract: Provided is an electronic component including: a base member; an electronic device fixed on the base member; and a lid member arranged over the electronic device and fixed on the base member. A primary material of the lid member is a crystal quartz, the lid member has two primary faces opposing to the electronic device and four side faces, and each of the four side faces is a wet-etched face that is not parallel to an optical axis of the crystal quartz.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: June 11, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yu Katase, Tadashi Kosaka, Koichi Shimizu, Shuichi Chiba, Kazuya Notsu, Yoshifumi Murakami
  • Patent number: 10108405
    Abstract: A memory stores first code that compares a value of a variable with each of three or more comparison values, and that performs branch control in accordance with comparison results. A processor determines a minimum comparison value and a maximum comparison value among the comparison values. The processor converts the first code into second code that compares the value of the variable with the minimum comparison value and the maximum comparison value, and that performs the branch control without performing comparisons with the other comparison values when the value of the variable is less than the minimum comparison value or greater than the maximum comparison value.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: October 23, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Takahiro Miyoshi, Shuichi Chiba
  • Publication number: 20180269336
    Abstract: Provided is an electronic component including: a base member; an electronic device fixed on the base member; and a lid member arranged over the electronic device and fixed on the base member. A primary material of the lid member is a crystal quartz, the lid member has two primary faces opposing to the electronic device and four side faces, and each of the four side faces is a wet-etched face that is not parallel to an optical axis of the crystal quartz.
    Type: Application
    Filed: March 7, 2018
    Publication date: September 20, 2018
    Inventors: Yu Katase, Tadashi Kosaka, Koichi Shimizu, Shuichi Chiba, Kazuya Notsu, Yoshifumi Murakami
  • Patent number: 9884710
    Abstract: A lid member for a press-through package, and a press-through package packing body using the same, includes a lid member which is not to be inadvertently torn, while tablets or capsules as its contents can be removed under a uniform opening strength by a predetermined force or more using fingers. The lid member of the packing body includes a resin film, an adhesive, an aluminum foil, and a thermal adhesive layer, in which tapered through holes are formed in the resin film. The resin film is laminated to the aluminum foil to reinforce the lid member so that the lid member is not to be inadvertently torn. When contents of a container are pushed out using fingers, the lid member is broken starting from the tapered through holes provided in the resin film, and so the contents can be easily taken out.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: February 6, 2018
    Assignee: TOYO ALUMINIUM KABUSHIKI KAISHA
    Inventors: Hiroyuki Nishikawa, Tomonobu Sekiguchi, Kazunori Yamada, Hiroshi Kubo, Masahiro Sato, Shuichi Chiba
  • Patent number: 9823911
    Abstract: A compiling apparatus generates a dependency tree representing dependency relations among a plurality of instructions included in first code. The compiling apparatus detects, from the dependency tree, a partial tree including a first instruction, a second instruction, and a third instruction that depends on the operation results of the first and second instructions, and rewrites the instructions corresponding to the partial tree to a set of instructions including a plurality of complex instructions each of which causes a processor to perform a complex operation including a plurality of operations. The compiling apparatus generates second code on the basis of the dependency tree and the set of instructions.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: November 21, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Shuichi Chiba
  • Publication number: 20170039044
    Abstract: A memory stores first code that compares a value of a variable with each of three or more comparison values, and that performs branch control in accordance with comparison results. A processor determines a minimum comparison value and a maximum comparison value among the comparison values. The processor converts the first code into second code that compares the value of the variable with the minimum comparison value and the maximum comparison value, and that performs the branch control without performing comparisons with the other comparison values when the value of the variable is less than the minimum comparison value or greater than the maximum comparison value.
    Type: Application
    Filed: June 27, 2016
    Publication date: February 9, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Takahiro Miyoshi, Shuichi Chiba
  • Publication number: 20160272397
    Abstract: A lid member for a press-through package, and a press-through package packing body using the same in which the lid member is not to be inadvertently torn, while tablets or capsules as its contents can be taken out under a uniform opening strength by a predetermined force or more using fingers. The lid member of the packing body includes a resin film, an adhesive, an aluminum foil, and a thermal adhesive layer, in which tapered through holes are formed in the resin film. The resin film is laminated to the aluminum foil to reinforce the lid member so that the lid member is not to be inadvertently torn, while, when contents of a container are pushed out using fingers, the lid member is broken starting from the tapered through holes provided in the resin film, and thus the contents can be easily taken out.
    Type: Application
    Filed: February 27, 2014
    Publication date: September 22, 2016
    Inventors: Hiroyuki NISHIKAWA, Tomonobu SEKIGUCHI, Kazunori YAMADA, Hiroshi KUBO, Masahiro SATO, Shuichi CHIBA
  • Patent number: 9395986
    Abstract: A compiling apparatus detects a plurality of branch instructions, each of which specifies execution of branch processing on the basis of a result of a comparison operation between integers and indicates the same jump destination, in a first code. The compiling apparatus converts the plurality of branch instructions into an instruction group having fewer branch instructions than the plurality of branch instructions by using logical and arithmetic instructions. The compiling apparatus generates a second code using the converted instruction group when the number of cycles of processing based on the converted instruction group is smaller than that based on the plurality of branch instructions.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: July 19, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takahiro Miyoshi, Shuichi Chiba, Tomoko Nikko
  • Patent number: 9256437
    Abstract: A computer-readable recording medium having stored therein a program for causing a computer to execute a digital signature process includes determining that a first specific instruction for executing parallel calculations of the same type, each calculation operating on a different piece of data, is generated by combining first and second instructions included in a first code, retrieving, from the first code, a third instruction for calculating data referenced by the first instruction and a fourth instruction for calculating data referenced by the second instruction, and selecting the third and fourth instructions as candidates of instructions to be combined with each other preferentially to generate a second specific instruction which is different from the first specific instruction.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: February 9, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takashi Arakawa, Shuichi Chiba
  • Patent number: 9213548
    Abstract: An information processing apparatus generates first and second trees representing a dependency relationship among instructions from first code. The information processing apparatus then adjusts the height of the shorter one of the first and second trees by inserting pseudo instructions that do not cause any difference in data before and after operation in the shorter tree, and also shuffles the order of instructions existing at the same depth from the root, according to operation types in at least one of the first and second trees. The information processing apparatus compares the first and second trees subjected to the height adjustment and the order shuffling with each other to determine combinations of an instruction of the first tree and an instruction of the second tree.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: December 15, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Shuichi Chiba, Takashi Arakawa
  • Publication number: 20150293768
    Abstract: A compiling apparatus detects a plurality of branch instructions, each of which specifies execution of branch processing on the basis of a result of a comparison operation between integers and indicates the same jump destination, in a first code. The compiling apparatus converts the plurality of branch instructions into an instruction group having fewer branch instructions than the plurality of branch instructions by using logical and arithmetic instructions. The compiling apparatus generates a second code using the converted instruction group when the number of cycles of processing based on the converted instruction group is smaller than that based on the plurality of branch instructions.
    Type: Application
    Filed: March 19, 2015
    Publication date: October 15, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Takahiro MIYOSHI, Shuichi Chiba, Tomoko Nikko
  • Patent number: 9141357
    Abstract: A compiler determines executability of loop fusion, for each of a plurality of loops existing in a code to be processed, based on performance information of a system where the code to be processed is executed and based on operands and number of data transfers executed inside each of the loops. Then, the compiler executes fusion of loop processing in accordance with a determination result of executability of the loop fusion.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: September 22, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Tomoko Nikko, Shuichi Chiba