Patents by Inventor Shuichi HAMAGUCHI

Shuichi HAMAGUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11894298
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: February 6, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masanori Tsutsumi, Naohiro Hosoda, Shuichi Hamaguchi, Kazuki Isozumi, Genta Mizuno, Yusuke Mukae, Ryo Nakamura, Yu Ueda
  • Publication number: 20220216145
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: Masanori TSUTSUMI, Naohiro HOSODA, Shuichi HAMAGUCHI, Kazuki ISOZUMI, Genta MIZUNO, Yusuke MUKAE, Ryo NAKAMURA, Yu UEDA
  • Patent number: 11289416
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: March 29, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masanori Tsutsumi, Naohiro Hosoda, Shuichi Hamaguchi, Kazuki Isozumi, Genta Mizuno, Yusuke Mukae, Ryo Nakamura, Yu Ueda
  • Publication number: 20210159167
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 27, 2021
    Inventors: Masanori TSUTSUMI, Naohiro HOSODA, Shuichi HAMAGUCHI, Kazuki ISOZUMI, Genta MIZUNO, Yusuke MUKAE, Ryo NAKAMURA, Yu Yu UEDA