Patents by Inventor Shuichi Horihata

Shuichi Horihata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device having a test mode for testing an operation state
    Publication number: 20040204891
    Abstract: A bit line equalize circuit equalizes one and the other of bit lines to one and the other of predetermined bit line potentials in response to activation of a bit line equalize signal, respectively. The one predetermined bit line potential on the one bit lines is higher than the other predetermined bit line potential on the other bit line. Thereby, a read error reflecting WL-BC(BL) shorting and WL-SC(SN) shorting can be detected further rapidly without increasing a circuit area.
    Type: Application
    Filed: September 4, 2003
    Publication date: October 14, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Shuichi Horihata, Kenji Tokami
  • Semiconductor memory device capable of reading/writing data from/into arbitrary memory cell in an input/output compression test mode
    Patent number: 5777933
    Abstract: A compression reading switch circuit is provided between a data equality/inequality determination circuit and compressed one data input/output terminal in a DRAM. In the I/O compression mode, desired data can be read out among output data DOT from the determination circuit and read data D01-D04 thereby specifying a defective memory cell among four memory cells.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: July 7, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shuichi Horihata, Hiroshi Akamatsu