Abstract: Disclosed is a structure of a semiconductor integrated circuit such as bipolar transistor, along with the fabrication thereof, in which an active device region such an intrinsic base is formed from, at least, the bottom of the groove formed in a semiconductor substrate, and this active device region and a low resistance electrode take-out region such an extrinsic base formed around the groove are connected favorably with each other.

Abstract: A semiconductor device such as a Bi-CMOS having vertical or lateral bipolar transistors and MOS transistors is disclosed. The MOS transistors include a gate electrode made of a first conductive thin film, and sidewall spacers formed on the sides of the gate electrode and consisting of at least one deposition film. The vertical bipolar transistors include an emitter electrode made of a second conductive thin film, and an emitter diffusion window formed in the deposition film which is disposed under the emitter electrode. The lateral bipolar transistors include a base width defining region for defining the base width, and an insulation film formed between the base width defining region and the collector and emitter, and consisting of the deposition film.

Abstract: In a semiconductor integrated circuit device using a field effect transistor, such as MOS, having the end part of the drain overlapped with the gate electrode, a novel gate-drain overlap structure of excellent performance and reliability is presented. A manufacturing method for this device is also presented.

Abstract: A method for fabricating a semiconductor device which is capable of enlarging diameter of crystal grain of a polycrystalline conductor by a heat treatment which is carried out after surface lower portion of the polycrystalline conductor is made amorphous with ion-implanting atoms in the polycrystalline conductor by predetermined accelerating energy to thereby improve the uniformity of size of crystal grain. By this method, the uniformity of impurity concentration distribution is improved in the polycrystalline conductor and also in the impurity diffusion area, and further, the uniformity of resistance of a resistor or conductor formed by the polycrystalline conductor is improved.

Abstract: A semiconductor device and a method of making a semiconductor device including a semiconductor substrate of p-type conductivity, a first semiconductor region of n.sup.+ -type conductivity selectively formed on the semiconductor substrate, a second semiconductor region of n-type conductivity formed insularly contacting on the first semiconductor region, a groove extending from a surface of the second semiconductor region spaced from the first semiconductor region to the vicinity of a surface of the first semiconductor region abutting the second semiconductor region, a conductive material charged into the groove, and a third semiconductor region of high impurity n-type conductivity disposed so as to connect a bottom of the groove with the surface of the first semiconductor region, whereby the conductive material in the groove and the third semiconductor region are used as low resistance current paths reaching from the surface of the second semiconductor region to the first semiconductor region.

Abstract: Disclosed is a method of fabricating a polycidegate in semiconductor device which has a step of forming a conductor film of polysilicon on a substrate, a step of forming an ion implanted layer by implanting nitrogen ions into the polysilicon conductor film, and a step of forming a low resistance conductor film of titanium on the non-monocyrstalline conductor film. When a field effect transistor is formed by this method, using titanium nitride and/or TiSi.sub.2 alloy of the polysilicon conductor and low resistance conductor of titanium by heat treatment as a gate electrode material, the thickness of the alloyed layer is uniform, and breakdown of the gate insulating film due to local diffusion of low resistance conductor is not induced. In other embodiments, oxygen ions and silicon ions are also employed to form thin layers of tunnel oxide and amorphous silicon, respectively.

Abstract: In a method for fabricating a favorable bipolar semiconductor device in which the extrinsic base and emitter diffusion holes are formed in self-alignment, an optimum structure between the extrinsic base and instrinsic base is realized. By controlling the concentration of the impurities in the extrinsic base, the base contact and emitter region can be finely formed in self-alignment, and occurence of damage or contamination in the intrinsic base region is inhibited.

Abstract: A method of manufacturing a semiconductor device which comprises a step of forming a first groove in a semiconductor layer, a step of filling the first groove with a first insulating film, a step of selectively etching the first insulating film in the first groove to form at least one second groove having a small width, and a step of filling the second groove with a second insulating film to form an isolation layer having a large width and substantially flush with the semiconductor layer.

Abstract: A method of manufacturing a semiconductor device which comprises a step of forming a first groove in a semiconductor layer, a step of filling the first groove with a first insulating film, a step of selectively etching the first insulating film in the first groove to form at least one second groove having a small width, and a step of filling the second groove with a second insulating film to form an isolation layer having a large width and substantially flush with the semiconductor layer.

Abstract: A method for manufacturing a semiconductor device which comprises the steps of forming a first groove in that portion of a semiconductor substrate where an isolation is to be formed; selectively forming a second groove narrower than the first groove in that surface region of the semiconductor substrate which is surrounded by said first groove; depositing a masking material over the whole surface of the semiconductor substrate with a thickness less than half the width of the first groove and greater than half the width of the second groove; aniotropically etching the deposited masking material to eliminate substantially its thickness, thus leaving the masking material on the side walls of the first groove and entirely in the second groove; introducing an impurity into the bottom of the first groove to form an impurity region; filling the first groove with an isolating material; and forming a semiconductor element in that section of the semiconductor substrate which is surrounded by an isolation consisting of t

Abstract: A method of manufacturing a semiconductor device which comprises a step of forming a first groove in a semiconductor layer, a step of filling the first groove with a first insulating film, a step of selectively etching the first insulating film in the first groove to form at least one second groove having a small width, and a step of filling the second groove with a second insulating film to form an isolation layer having a large width and substantially flush with the semiconductor layer.

Abstract: A method for forming a groove in a semiconductor substrate is disclosed. The groove is formed in two steps. In the first step, a first shallow groove is formed in the semiconductor substrate and then a first mask pattern is selectively formed on the wall of the first groove. A second groove is formed in the bottom surface of the first groove using the first mask pattern as a mask. Subsequently the first mask is etched off. The obtained groove may be buried with an insulating material or an electrode material.

Abstract: The invention provides a method for manufacturing a semiconductor device, comprising the steps of: forming a mask material pattern at least on a portion of a semiconductor layer which corresponds to a prospective element formation region; etching the semiconductor layer, using the mask material pattern, to form a first groove which is wide and shallow; burying a first isolating material in the first groove to a thickness substantially equal to the depth of the first groove; etching a portion of the first isolating material film which is located in the vicinity of the prospective element formation region to partially expose a bottom of the first groove, thereby forming a second groove which is narrower than said first groove, a position of the second groove being defined by the mask material pattern; forming a third groove which is deeper than said first and second grooves by etching a bottom of the second groove; and burying a second isolating material in the third groove.

Abstract: A method of manufacturing a semiconductor device wherein grooves are formed between vertical type-npn transistors and insulating oxide layers are formed on the bottoms of the grooves, thereby preventing parasitic p-n junctions, which is characterized in that said grooves are formed by using as a mask a conductive pattern containing an impurity for forming an impurity region or by using as a mask an insulating film formed by the annealing of the conductive pattern.

Abstract: A method for manufacturing a semiconductor integrated circuit device having a plurality of bipolar transistors is characterized in that, using an antioxidant insulation film pattern as a mask, an underlying conductive layer is overetched to form a conductive layer pattern; the antioxidant insulation film pattern is of overhanging structure with respect to the conductive pattern; a first thermally oxidized film is grown on the circumferential surface of the conductive layer pattern and a second thermally oxidized film is formed on the exposed part of a semiconductor substrate or semiconductor layer; and the second thermally oxidized film on the semiconductor substrate or the semiconductor layer is anisotropicetched away using the antioxidant insulation film pattern as a mask.