Patents by Inventor Shuichi KATSUI

Shuichi KATSUI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11842002
    Abstract: To provide an inexpensive display device. The display device includes a pixel and an IC chip. The pixel includes a first pixel circuit including a display element and a second pixel circuit including a light-receiving device. The one IC chip includes a control circuit, a data driver circuit, and a read circuit. The first and second pixel circuits are electrically connected to the read circuit. The control circuit has a function of controlling driving of the data driver circuit and the read circuit. The data driver circuit has a function of supplying image data to the first pixel circuit. The read circuit has a function of outputting a monitor signal corresponding to a monitor current when the monitor current flows through the first pixel circuit. The read circuit also has a function of outputting an imaging signal corresponding to imaging data acquired by the second pixel circuit.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: December 12, 2023
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kei Takahashi, Hidetomo Kobayashi, Hajime Kimura, Takeshi Osada, Hideaki Shishido, Kiyotaka Kimura, Shuichi Katsui, Takeya Hirose, Takayuki Ikeda
  • Publication number: 20230386383
    Abstract: A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.
    Type: Application
    Filed: April 6, 2023
    Publication date: November 30, 2023
    Inventors: Takashi NAKAGAWA, Takayuki IKEDA, Hidetomo KOBAYASHI, Hideaki SHISHIDO, Shuichi KATSUI, Kiyotaka KIMURA
  • Patent number: 11814126
    Abstract: To provide a driver alert system capable of improving the safety. A bicycle includes a first transmission circuit transmitting a first ultrasonic wave, a first receiving circuit receiving a second ultrasonic wave, an arithmetic circuit detecting the presence or absence of an object from the second ultrasonic wave, and a second transmission circuit transmitting a third ultrasonic wave. A driver wears a second housing including a second receiving circuit receiving the third ultrasonic wave. The arithmetic circuit includes a first selection circuit selecting a potential based on the second ultrasonic wave at a different timing, a plurality of signal retention circuits retaining a potential based on the second ultrasonic wave, a second selection circuit selecting any one of the plurality of signal retention circuits, and a signal processing circuit to which a signal selected in and output from the second selection circuit is input.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: November 14, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shuichi Katsui, Takayuki Ikeda
  • Patent number: 11626052
    Abstract: A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: April 11, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Nakagawa, Takayuki Ikeda, Hidetomo Kobayashi, Hideaki Shishido, Shuichi Katsui, Kiyotaka Kimura
  • Publication number: 20220350432
    Abstract: To provide an inexpensive display device. The display device includes a pixel and an IC chip. The pixel includes a first pixel circuit including a display element and a second pixel circuit including a light-receiving device. The one IC chip includes a control circuit, a data driver circuit, and a read circuit. The first and second pixel circuits are electrically connected to the read circuit. The control circuit has a function of controlling driving of the data driver circuit and the read circuit. The data driver circuit has a function of supplying image data to the first pixel circuit. The read circuit has a function of outputting a monitor signal corresponding to a monitor current when the monitor current flows through the first pixel circuit. The read circuit also has a function of outputting an imaging signal corresponding to imaging data acquired by the second pixel circuit.
    Type: Application
    Filed: September 22, 2020
    Publication date: November 3, 2022
    Inventors: Kei TAKAHASHI, Hidetomo KOBAYASHI, Hajime KIMURA, Takeshi OSADA, Hideaki SHISHIDO, Kiyotaka KIMURA, Shuichi KATSUI, Takeya HIROSE, Takayuki IKEDA
  • Publication number: 20220230573
    Abstract: A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.
    Type: Application
    Filed: April 28, 2020
    Publication date: July 21, 2022
    Inventors: Takashi NAKAGAWA, Takayuki IKEDA, Hidetomo KOBAYASHI, Hideaki SHISHIDO, Shuichi KATSUI, Kiyotaka KIMURA
  • Publication number: 20220208939
    Abstract: A display device with high resolution is provided. A display device with low power consumption is provided. A display device with high luminance is provided. A display device with a high aperture ratio is provided. The display device includes a first wiring, a second wiring, a third wiring, and a pixel electrode. The first wiring extends in a first direction and is supplied with a source signal. The second wiring extends in a second direction intersecting the first direction and is supplied with a gate signal. The third wiring is supplied with a constant potential. The first wiring and the pixel electrode overlap with each other with the third wiring therebetween.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 30, 2022
    Inventors: Hidetomo KOBAYASHI, Hideaki SHISHIDO, Shuichi KATSUI
  • Publication number: 20220181428
    Abstract: A display apparatus with low power consumption and high image quality is provided. The display apparatus includes a light-emitting element, a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. Preferably, one electrode of the light-emitting element is electrically connected to one of a source and a drain of the first transistor; the one electrode of the light-emitting element is electrically connected to one electrode of the first capacitor; a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor; the gate of the first transistor is electrically connected to one electrode of the second capacitor; the other electrode of the second capacitor is electrically connected to the other electrode of the first capacitor; and the other electrode of the second capacitor is electrically connected to one of a source and a drain of the third transistor.
    Type: Application
    Filed: April 27, 2020
    Publication date: June 9, 2022
    Inventors: Hidetomo KOBAYASHI, Hideaki SHISHIDO, Takayuki IKEDA, Shuichi KATSUI
  • Patent number: 11335813
    Abstract: A semiconductor device in which the accuracy of arithmetic operation is increased by correction of the threshold voltage of a transistor can be provided. The semiconductor device includes first and second current supply circuits, and the second current supply circuit has the same configuration as the first current supply circuit. The first current supply circuit includes first and second transistors, a first capacitor, and first to third nodes. A first terminal of the first transistor is electrically connected to the first node, and a back gate of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the first capacitor. A gate of the first transistor is electrically connected to the second node, and a second terminal of the first capacitor is electrically connected to a second terminal of the first transistor.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: May 17, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hidetomo Kobayashi, Takayuki Ikeda, Takashi Nakagawa, Takeya Hirose, Shuichi Katsui
  • Publication number: 20220041242
    Abstract: To provide a driver alert system capable of improving the safety. A bicycle includes a first transmission circuit transmitting a first ultrasonic wave, a first receiving circuit receiving a second ultrasonic wave, an arithmetic circuit detecting the presence or absence of an object from the second ultrasonic wave, and a second transmission circuit transmitting a third ultrasonic wave. A driver wears a second housing including a second receiving circuit receiving the third ultrasonic wave. The arithmetic circuit includes a first selection circuit selecting a potential based on the second ultrasonic wave at a different timing, a plurality of signal retention circuits retaining a potential based on the second ultrasonic wave, a second selection circuit selecting any one of the plurality of signal retention circuits, and a signal processing circuit to which a signal selected in and output from the second selection circuit is input.
    Type: Application
    Filed: October 1, 2019
    Publication date: February 10, 2022
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shuichi KATSUI, Takayuki IKEDA
  • Publication number: 20210318856
    Abstract: A semiconductor device that updates a weight coefficient used for arithmetic operation by an artificial neural network is provided. Each of the first to third memory cells draws a current corresponding to data of its retention node and changes the data in accordance with the potentials of first and second wirings. When a weight coefficient and first and second reference data are held in the retention nodes of the first to third memory cells, the first circuit supplies, to a third wiring, a constant currents drawn by the second and third memory cells. When input data is input to the first wiring, a difference current between the constant current and a current drawn by the first memory cell is changed, and the second circuit outputs arithmetic result data corresponding to the change. The third circuit inputs update data corresponding to the arithmetic result data to the second wiring.
    Type: Application
    Filed: April 15, 2019
    Publication date: October 14, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takayuki IKEDA, Roh YAMAMOTO, Shuichi KATSUI
  • Publication number: 20210217891
    Abstract: A semiconductor device in which the accuracy of arithmetic operation is increased by correction of the threshold voltage of a transistor can be provided. The semiconductor device includes first and second current supply circuits, and the second current supply circuit has the same configuration as the first current supply circuit. The first current supply circuit includes first and second transistors, a first capacitor, and first to third nodes. A first terminal of the first transistor is electrically connected to the first node, and a back gate of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the first capacitor. A gate of the first transistor is electrically connected to the second node, and a second terminal of the first capacitor is electrically connected to a second terminal of the first transistor.
    Type: Application
    Filed: May 23, 2019
    Publication date: July 15, 2021
    Inventors: Hidetomo KOBAYASHI, Takayuki IKEDA, Takashi NAKAGAWA, Takeya HIROSE, Shuichi KATSUI