Patents by Inventor Shuichi Komatsu

Shuichi Komatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11383523
    Abstract: A print head drive circuit outputs an output signal from a terminal electrically coupled to a low voltage logic signal input terminal to which a low voltage logic signal is input and has a first mode in which the print head drive circuit controls a print head to execute reading processing of reading information stored in a memory and not to execute ejection control processing of controlling whether or not to supply a high voltage signal to an ejecting portion group by switching a switch group in accordance with the output signal and a second mode in which the print head drive circuit controls the print head not to execute the reading processing and to execute the ejection control processing in accordance with the output signal.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: July 12, 2022
    Inventors: Eiji Takagi, Masanori Koizumi, Shunya Komatsu, Shuichi Nakano, Masashi Kamiyanagi, Toru Matsuyama
  • Publication number: 20180178343
    Abstract: Grinding is performed on an outer peripheral surface of a shaft member while rotationally driving the shaft member under a state in which both end surfaces of the shaft member are sandwiched between a pair of support portions. A convex surface is formed on one axial end surface of the shaft member or an end surface of one of the pair of support portions, and a flat surface is formed on the other of the one axial end surface of the shaft member and the end surface of the one of the pair of support portions. The flat surface and an apex of the convex surface are brought into contact with each other to support one axial end portion of the shaft member.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Inventors: Jun HIRADE, Shuichi KOMATSU
  • Patent number: 9931725
    Abstract: Grinding is performed on an outer peripheral surface of a shaft member while rotationally driving the shaft member under a state in which both end surfaces of the shaft member are sandwiched between a pair of support portions. A convex surface is formed on one axial end surface of the shaft member or an end surface of one of the pair of support portions, and a flat surface is formed on the other of the one axial end surface of the shaft member and the end surface of the one of the pair of support portions. The flat surface and an apex of the convex surface are brought into contact with each other to support one axial end portion of the shaft member.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: April 3, 2018
    Assignee: NTN CORPORATION
    Inventors: Jun Hirade, Shuichi Komatsu
  • Publication number: 20160176005
    Abstract: Grinding is performed on an outer peripheral surface of a shaft member (2) while rotationally driving the shaft member (2) under a state in which both end surfaces of the shaft member (2) are sandwiched between a pair of support portions (a backing plate (74) and a pressure plate (75)). A convex surface (2a6) is formed on one axial end surface of the shaft member by swelling an inner-diameter portion thereof, and a flat surface is formed on an end surface (75a) of the pressure plate (75) configured to support the convex surface in a contact manner. The end surface (75a) of the pressure plate (75) and an apex (2a7) of the convex surface (2a6) of the shaft member (2) are brought into contact with each other to support one axial end portion of the shaft member (2).
    Type: Application
    Filed: July 29, 2014
    Publication date: June 23, 2016
    Inventors: Jun HIRADE, Shuichi KOMATSU
  • Patent number: 7233846
    Abstract: An enlargement button that instruct enlargement of first to fourth buttons to is displayed on a display. The first to fourth buttons to are used to instruct the operation of a control device to be controlled by an electronic control unit to which a trouble diagnosing device is connected. When the enlargement button is manipulated, the first to fourth buttons to are enlarged in the display respectively in corners sections created by dividing the display screen substantially equally into four. With this arrangement, the operator no longer needs to monitor the first to the fourth button by eyes for manipulating these buttons, thereby improving the operability.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: June 19, 2007
    Assignee: Mitsubishi Fuso Truck and Bus Corporation
    Inventors: Hiroshi Kawauchi, Akihisa Kitajima, Shuichi Komatsu, Tomonari Miura
  • Publication number: 20060081995
    Abstract: A soldered material according to an aspect of the present invention comprises a first metallic material to be soldered, a second metallic material to be soldered which is composed of at least one element selected from the group consisting of nickel, palladium, platinum and aluminum, and a soldering layer soldering the first metallic material and the second metallic material, and in a cross-sectional microstructure of the soldering layer a solid solution phase comprising the element constituting the second metallic material and tin is present.
    Type: Application
    Filed: July 8, 2005
    Publication date: April 20, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshihide Takahashi, Shuichi Komatsu, Masahiro Tadauchi, Kazutaka Matsumoto, Izuru Komatsu
  • Publication number: 20050065680
    Abstract: An enlargement button that instruct enlargement of first to fourth buttons to is displayed on a display. The first to fourth buttons to are used to instruct the operation of a control device to be controlled by an electronic control unit to which a trouble diagnosing device is connected. When the enlargement button is manipulated, the first to fourth buttons to are enlarged in the display respectively in corners sections created by dividing the display screen substantially equally into four. With this arrangement, the operator no longer needs to monitor the first to the fourth button by eyes for manipulating these buttons, thereby improving the operability.
    Type: Application
    Filed: August 4, 2004
    Publication date: March 24, 2005
    Inventors: Hiroshi Kawauchi, Akihisa Kitajima, Shuichi Komatsu, Tomonari Miura
  • Patent number: 5952687
    Abstract: A semiconductor memory device having a semiconductor substrate, an insulating layer provided on the substrate, and a memory cell. The memory cell has a switching transistor provided on the substrate and a charge storage element in a trench made in the insulating layer. The charge storage element has a bottom electrode, a dielectric layer and a top electrode deposited one on another in the order mentioned.
    Type: Grant
    Filed: July 8, 1997
    Date of Patent: September 14, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Kawakubo, Kazuhiro Eguchi, Shuichi Komatsu, Kazuhide Abe
  • Patent number: 5929473
    Abstract: An SiO.sub.2 film and a first wiring layer are arranged in this order on a GaAs substrate. A capacitor is formed on the first wiring layer. The capacitor includes a lower electrode which has a multi-layer structure consisting of a Ti layer, an Mo layer, and a Pt layer in this order from underside. The capacitor also includes a dielectric film made of strontium titanate. The capacitor further includes an upper electrode which has a multi-layer structure consisting of a WN.sub.x layer (120 nm) and a W layer (300 nm) in this order from underside. That surface of the upper electrode, which is in contact with the dielectric film, is defined by the tungsten nitride layer.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: July 27, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nishihori, Yoshiaki Kitaura, Yoshikazu Tanabe, Tomonori Aoyama, Kyoichi Suguro, Kumi Okuwada, Shuichi Komatsu, Kazuhide Abe
  • Patent number: 5889299
    Abstract: A thin film capacitor including a first electrode having on its surface a (100) face of cubic system or a (001) face of tetragonal system, a dielectric thin film epitaxially grown on the first electrode and exhibiting a crystal structure which inherently belongs to a perovskite structure of cubic system, and a second electrode formed on the dielectric thin film. Further, the dielectric thin film meets the following relationship V/V.sub.0 .gtoreq.1.01 where a unit lattice volume of true perovskite crystal structure belonging to the cubic system (lattice constant a.sub.0) is represented by V.sub.0 =a.sub.0.sup.3, and a unit lattice volume (lattice constant a=b.noteq.c) which is strained toward a tetragonal system after the epitaxial growth is represented by V=a.sup.2 c, and also meets the following relationship c/a.gtoreq.1.01 where c/a represents a ratio between a lattice constant "c" in the direction thicknesswise of the film and a lattice constant "a" in the direction parallel with a plane of the film.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: March 30, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhide Abe, Shuichi Komatsu, Mitsuaki Izuha, Noburu Fukushima, Kenya Sano, Takashi Kawakubo
  • Patent number: 5760432
    Abstract: A capacitor having a first electrode and a dielectric material epitaxially deposited on a surface of the electrode to form a dielectric layer on the electrode. The dielectric material forming the dielectric layer has induced strain in the layer sufficient to significantly improve the dielectric properties. A second electrode is placed on the dielectric layer.
    Type: Grant
    Filed: April 7, 1995
    Date of Patent: June 2, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhide Abe, Shuichi Komatsu, Kazuhiro Eguchi, Takashi Kawakubo
  • Patent number: 5739563
    Abstract: A semiconductor memory device comprising a silicon substrate, a plurality of switching transistors formed on the silicon substrate, an insulating layer having an opening and formed on a surface portion of the silicon substrate where the plurality of switching transistors formed, and a plurality of capacitors for accumulating electric charge formed on the insulating layer and connected respectively to the switching transistors via a conductive film buried in the opening of insulating layer, wherein each of the capacitors for accumulating electric charge is provided with an underlying crystal layer formed on the insulating layer and with a dielectric film consisting essentially of a ferroelectric material and epitaxially or orientationaly grown on the underlying crystal layer, and the switching transistors and the capacitors for accumulating electric charge connected to each other constitute a plurality of memory cells arranged in a two-dimensional pattern.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: April 14, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Kawakubo, Kenya Sano, Kazuhide Abe, Shuichi Komatsu, Noburu Fukushima, Kazuhiro Eguchi
  • Patent number: 5691219
    Abstract: A semiconductor memory device having a semiconductor substrate, an insulating layer provided on the substrate, and a memory cell. The memory cell has a switching transistor provided on the substrate and a charge storage element in a trench made in the insulating layer. The charge storage element has a bottom electrode, a dielectric layer and a top electrode deposited one on another in the order mentioned.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: November 25, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Kawakubo, Kazuhiro Eguchi, Shuichi Komatsu, Kazuhide Abe
  • Patent number: 5670808
    Abstract: A semiconductor device in which an SiO.sub.2 film and a first wiring layer are arranged in this order on a GaAs substrate. A capacitor is formed on the first wiring layer. The capacitor includes a lower electrode which has a multi-layer structure consisting of a Ti layer, an Mo layer, and a Pt layer in this order from underside. The capacitor also includes a dielectric film made of strontium titanate. The capacitor further includes an upper electrode which has a multi-layer structure consisting of a WN.sub.x layer (120 um) and a W layer (300 nm) in this order from underside. That surface of the upper electrode, which is in contact with the dielectric film, is defined by the tungsten nitride layer.
    Type: Grant
    Filed: January 25, 1996
    Date of Patent: September 23, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nishihori, Yoshiaki Kitaura, Yoshikazu Tanabe, Tomonori Aoyama, Kyoichi Suguro, Kumi Okuwada, Shuichi Komatsu, Kazuhide Abe
  • Patent number: 5498909
    Abstract: The close-packed plane of a single crystal forming an electrode line such as electrodes or lines of a semiconductor device whose active regions are reduced in size, i.e., highly integrated, is arranged parallel to the longitudinal direction of the line; or in the case of a polycrystalline electrode line, the angle formed between the normal line direction of the close-packed plane of its crystal grains and that of the electrode line is arranged to be 80.degree. or less.
    Type: Grant
    Filed: August 31, 1992
    Date of Patent: March 12, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Hasunuma, Hisashi Kaneko, Atsuhito Sawabe, Takashi Kawanoue, Yoshiko Kohanawa, Shuichi Komatsu
  • Patent number: 5187561
    Abstract: The close-packed plane of a single crystal forming an electrode line such as electrodes or lines of a semiconductor device whose active regions are reduced in size, i.e., highly integrated, is arranged parallel to the longitudinal direction of the line; or in the case of a polycrystalline electrode line, the angle formed between the normal line direction of the close-packed plane of its crystal grains and that of the electrode line is arranged to be 80.degree. or less.
    Type: Grant
    Filed: June 29, 1990
    Date of Patent: February 16, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Hasunuma, Hisashi Kaneko, Atsuhito Sawabe, Takashi Kawanoue, Yoshiko Kohanawa, Shuichi Komatsu
  • Patent number: 4922462
    Abstract: In a reversible memory system, a pulsed laser beam generated from a laser unit is directed to a recording layer formed on a substrate 1. The recording layer essentially consists of a recording medium, for example, an iron-nickel alloy containing iron as a major component and 27 to 30 atomic % of nickel, which undergoes martensite transformation from a low-temperature phase to a high-temperature phase at a predetermined temperature Af and which undergoes a stress-induced transformation at a characteristic temperature Md. When a region of the recording layer is irradiated with the laser beam having a predetermined intensity, the region undergoes a stress-induced transformation so that the region is changed from the high temperature phase to the low temperature phase.
    Type: Grant
    Filed: November 9, 1988
    Date of Patent: May 1, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sumio Ikegawa, Yoshiaki Terashima, Nobuaki Yasuda, Katsutarou Ichihara, Shuichi Komatsu, Shinji Arai
  • Patent number: 4855992
    Abstract: There is disclosed a bubble-mode data-rewritable optical disc, which has a transparent substrate and a recording layer, formed on the substrate, for storing data to be optically rewritable. The substrate is at least partially formed of an organic material, which releases a gas component when it is heated at a radiation region of a data recording light beam. The recording layer is deposited on the substrate by co-sputtering or co-vacuum evaporation. The recording layer is made of a specific amorphous material containing silicon and fine metal particles. When the gas component is released from the substrate, the recording layer is deformed to be locally peeled off out of the substrate by pressure of the gas component, thus forming a protuberance. In a data erasing mode, a data erasing light beam is radiated onto the recording layer, which is then deformed so as to cause the protuberance to disappear, and has a substantially flat surface, thereby erasing the stored information.
    Type: Grant
    Filed: December 23, 1987
    Date of Patent: August 8, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sumio Ikegawa, Akio Hori, Shuichi Komatsu, Shinji Arai, Nobuaki Yasuda
  • Patent number: 4839861
    Abstract: A rewritable information recording medium which has a recording layer containing a Group I transition element and a Group IV representative elements of the Periodic Table as two principal element and a support substrate for physically supporting the recording layer, and an information-write, -read, and erase method using this recording medium. When the recording layer is immediately cooled after it is heated up to near a eutectic temperature of the two principal elements, two metastable phases having different energy levels appear. A state in the first metastable phase of the higher energy level has a reflectivity sufficiently higher than that of a state of a mixed phase including the second metastable phase of the lower energy level, or that of the equilibrium state. The state in the first metastable phase can be obtained by heating a recording layer in another state by light beam irradiation.
    Type: Grant
    Filed: February 6, 1987
    Date of Patent: June 13, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sumio Ikegawa, Shuichi Komatsu, Shinji Arai, Sumio Ashida, Nobuaki Yasuda
  • Patent number: 4757492
    Abstract: A method for recording and reproducing information on or from an optical recording medium, which comprises:recording information by illuminating light to the optical recording medium which is equipped as a recording film with a thin film comprising dispersed fine grains of a material capable of showing a metal-insulator transition to cause the metal-insulator transition owing to the heating effect of the light; and reproducing the information by utilizing changes in optical characteristics owing to a plasma resonance absorption by the fine grains dispersed in the thin film. The method of this invention permits high-density recording with high sensitivity and upon reproduction, enables reproduction of record with a high signal/noise ratio. The recording medium obtained by this method is an erasable optical recording medium, which permits its reutilization for recording and reproduction after erasure of the previously-stored record.
    Type: Grant
    Filed: December 4, 1985
    Date of Patent: July 12, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noburu Fukushima, Hisashi Yoshino, Masashi Sahashi, Shuichi Komatsu