Patents by Inventor Shuichi Kubouchi
Shuichi Kubouchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9543037Abstract: To provide an electrical fuse that is connected to a detection node via a selective transistor, a precharge transistor that precharges the detection node in a state where the selective transistor is off; a bias transistor that passes a bias current to the detection node in a state where the selective transistor is on and the precharge transistor is off, and a detection circuit that detects a potential of the detection node in a state where the bias current is flowing into the detection node, wherein the bias transistor reduces an amount of the bias current in a stepwise manner or a continuous manner.Type: GrantFiled: November 15, 2011Date of Patent: January 10, 2017Assignee: Longitude Semiconductor S.A.R.L.Inventors: Shuichi Kubouchi, Daiki Nakashima
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Patent number: 9230686Abstract: Disclosed herein is an apparatus that includes: a plurality of memory banks each including a plurality of memory cells; a plurality of redundant circuits each allocated to an associated one of the plurality of memory banks to replace a defective memory cell among the plurality of memory cells included in the associated memory bank; a plurality of roll call circuits allocated to an associated one of the plurality of memory banks to generate a roll call data when an address corresponding to the defective memory cell is supplied; and a plurality of data buses commonly allocated to the plurality of memory banks. The roll call circuits output the roll call data to the plurality of data buses in parallel.Type: GrantFiled: March 24, 2014Date of Patent: January 5, 2016Assignee: Micron Technology, Inc.Inventors: Shuichi Kubouchi, Hiroyuki Yamamoto
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Publication number: 20140286113Abstract: Disclosed herein is an apparatus that includes: a plurality of memory banks each including a plurality of memory cells; a plurality of redundant circuits each allocated to an associated one of the plurality of memory banks to replace a defective memory cell among the plurality of memory cells included in the associated memory bank; a plurality of roll call circuits allocated to an associated one of the plurality of memory banks to generate a roll call data when an address corresponding to the defective memory cell is supplied; and a plurality of data buses commonly allocated to the plurality of memory banks. The roll call circuits output the roll call data to the plurality of data buses in parallel.Type: ApplicationFiled: March 24, 2014Publication date: September 25, 2014Applicant: Micron Technology, Inc.Inventors: SHUICHI KUBOUCHI, Hiroyuki Yamamoto
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Publication number: 20140111271Abstract: A semiconductor device includes a boosting circuit that boosts an internal power supply voltage in a boosting range according to an external power supply voltage, an external voltage-level comparison circuit that compares the external power supply voltage and a predetermined reference voltage, and a variable resistor circuit that includes a variable resistor connected to an output terminal of the boosting circuit. The variable resistor circuit controls a resistance value of the variable resistor based on a comparison result of the external voltage-level comparison circuit.Type: ApplicationFiled: December 27, 2013Publication date: April 24, 2014Applicant: Elpida Memory, Inc.Inventors: Hiroki FUJISAWA, Shuichi KUBOUCHI, Hitoshi TANAKA
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Patent number: 8699256Abstract: A bit memory circuit of an antifuse element set includes two antifuse elements of which logical states are changed from an insulation state to a conductive state when a program voltage is applied. 1-bit data is represented by the logical states of the two antifuse elements. The two antifuse elements are collectively controlled by one decoder circuit. When writing data, the decoder circuit simultaneously performs insulation-breakdown on the two antifuse elements by simultaneously connecting the two antifuse elements to program voltage lines, respectively.Type: GrantFiled: September 7, 2010Date of Patent: April 15, 2014Assignee: Elpida Memory, Inc.Inventors: Shuichi Kubouchi, Hiroki Fujisawa
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Patent number: 8633758Abstract: A semiconductor device includes a boosting circuit that boosts an internal power supply voltage in a boosting range according to an external power supply voltage, an external voltage-level comparison circuit that compares the external power supply voltage and a predetermined reference voltage, and a variable resistor circuit that includes a variable resistor connected to an output terminal of the boosting circuit. The variable resistor circuit controls a resistance value of the variable resistor based on a comparison result of the external voltage-level comparison circuit.Type: GrantFiled: March 11, 2011Date of Patent: January 21, 2014Assignee: Elpida Memory, Inc.Inventors: Hiroki Fujisawa, Shuichi Kubouchi, Hitoshi Tanaka
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Patent number: 8270237Abstract: To provided a relief-address generating circuit that generates relief address information based on plural data bits supplied in time sequence via a first terminal from outside and a programming circuit that writes into any one of fuse sets the relief address information generated by the relief-address generating circuit. With this configuration, repetition of a programming operation by the total number of the fuse sets at the maximum completes a series of write processing on relief address information. Therefore, it is possible to reduce the time required for a series of write processing on relief address information.Type: GrantFiled: September 10, 2010Date of Patent: September 18, 2012Assignee: Elpida Memory, Inc.Inventor: Shuichi Kubouchi
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Publication number: 20120120735Abstract: To provide a plurality of fuse elements, each of which is either in a programmed state or a non-programmed state, a plurality of fuse determination circuits, each of which outputs a determination result signal that corresponds to a programmed state or a non-programmed state of the fuse element, and a plurality of latch circuits that commonly receive a first timing signal, and each of which latches and outputs the determination result signal synchronously with the first timing signal.Type: ApplicationFiled: November 16, 2011Publication date: May 17, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Shuichi KUBOUCHI, Daiki NAKASHIMA
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Publication number: 20120120750Abstract: To provide an electrical fuse that is connected to a detection node via a selective transistor, a precharge transistor that precharges the detection node in a state where the selective transistor is off; a bias transistor that passes a bias current to the detection node in a state where the selective transistor is on and the precharge transistor is off, and a detection circuit that detects a potential of the detection node in a state where the bias current is flowing into the detection node, wherein the bias transistor reduces an amount of the bias current in a stepwise manner or a continuous manner.Type: ApplicationFiled: November 15, 2011Publication date: May 17, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Shuichi KUBOUCHI, Daiki NAKASHIMA
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Publication number: 20110221513Abstract: A semiconductor device includes a boosting circuit that boosts an internal power supply voltage in a boosting range according to an external power supply voltage, an external voltage-level comparison circuit that compares the external power supply voltage and a predetermined reference voltage, and a variable resistor circuit that includes a variable resistor connected to an output terminal of the boosting circuit. The variable resistor circuit controls a resistance value of the variable resistor based on a comparison result of the external voltage-level comparison circuit.Type: ApplicationFiled: March 11, 2011Publication date: September 15, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Hiroki Fujisawa, Shuichi Kubouchi, Hitoshi Tanaka
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Patent number: 7940587Abstract: A semiconductor memory device comprises a memory cell array having memory cells arranged at intersections of word lines and bit lines, a first sense amplifier connected to a bit line at a predetermined position of the bit lines, a second sense amplifier connected to a bit line adjacent to the bit line at the predetermined position, a supplying circuit for supplying a predetermined voltage to each bit line connected to the first or second sense amplifier, and a sense amplifier control circuit capable of controlling the first and second sense amplifiers independently. In the semiconductor memory device, the sense amplifier control circuit performs a control in which an operation of either of the first and second sense amplifiers is stopped, the predetermined voltage is supplied to the bit line connected to the stopped sense amplifier, and the other of the first and second sense amplifiers is operated.Type: GrantFiled: April 20, 2009Date of Patent: May 10, 2011Assignee: Elpida Memory Inc.Inventors: Shuichi Kubouchi, Jun Suzuki
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Patent number: 7940583Abstract: There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.Type: GrantFiled: February 6, 2009Date of Patent: May 10, 2011Assignee: Elpida Memory, Inc.Inventors: Yoshiro Riho, Jun Suzuki, Yasuhiro Matsumoto, Shuichi Kubouchi, Hiromasa Noda, Yasuji Koshikawa
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Publication number: 20110096616Abstract: A sense amplifier circuit, which is connected to a bit line and to an inverted bit line to which a voltage, inverted alternatively from a high level or a low level of a voltage applied to the bit line, is applied, includes a first resistance section reducing a voltage output from a memory cell through the inverted bit line, a second resistance section reducing a voltage output from a memory cell through the bit line, and an amplification section amplifying the first voltage reduced by the first resistance section and amplifying the second voltage reduced by the second resistance section.Type: ApplicationFiled: October 14, 2010Publication date: April 28, 2011Inventors: Shuichi KUBOUCHI, Yoshiro RIHO
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Publication number: 20110063933Abstract: To provided a relief-address generating circuit that generates relief address information based on plural data bits supplied in time sequence via a first terminal from outside and a programming circuit that writes into any one of fuse sets the relief address information generated by the relief-address generating circuit. With this configuration, repetition of a programming operation by the total number of the fuse sets at the maximum completes a series of write processing on relief address information. Therefore, it is possible to reduce the time required for a series of write processing on relief address information.Type: ApplicationFiled: September 10, 2010Publication date: March 17, 2011Applicant: Elpida Memory, Inc.Inventor: Shuichi Kubouchi
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Publication number: 20110058402Abstract: A bit memory circuit of an antifuse element set includes two antifuse elements of which logical states are changed from an insulation state to a conductive state when a program voltage is applied. 1-bit data is represented by the logical states of the two antifuse elements. The two antifuse elements are collectively controlled by one decoder circuit. When writing data, the decoder circuit simultaneously performs insulation-breakdown on the two antifuse elements by simultaneously connecting the two antifuse elements to program voltage lines, respectively.Type: ApplicationFiled: September 7, 2010Publication date: March 10, 2011Applicant: Elpida Memory, Inc.Inventors: Shuichi Kubouchi, Hiroki Fujisawa
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Publication number: 20100103758Abstract: To provide a first power supply wiring that supplies a lower-side write potential to a sense amplifier, a second power supply wiring that supplies a higher-side write potential to the sense amplifier, a third power supply wiring that supplies an overdrive potential to the sense amplifier, and a stabilizing capacitance arranged between the first power supply wiring and the third power supply wiring. With this configuration, a capacitance value applied to the lower-side write potential and a capacitance value applied to the overdrive potential inevitably match, and thus fluctuation of the lower-side write potential and fluctuation of the overdrive potential at an initial stage of a sense operation are offset.Type: ApplicationFiled: October 26, 2009Publication date: April 29, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Yoshiro Riho, Shuichi Kubouchi
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Publication number: 20090268534Abstract: A semiconductor memory device comprises a memory cell array having memory cells arranged at intersections of word lines and bit lines, a first sense amplifier connected to a bit line at a predetermined position of the bit lines, a second sense amplifier connected to a bit line adjacent to the bit line at the predetermined position, a supplying circuit for supplying a predetermined voltage to each bit line connected to the first or second sense amplifier, and a sense amplifier control circuit capable of controlling the first and second sense amplifiers independently. In the semiconductor memory device, the sense amplifier control circuit performs a control in which an operation of either of the first and second sense amplifiers is stopped, the predetermined voltage is supplied to the bit line connected to the stopped sense amplifier, and the other of the first and second sense amplifiers is operated.Type: ApplicationFiled: April 20, 2009Publication date: October 29, 2009Inventors: Shuichi Kubouchi, Jun Suzuki
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Patent number: 7580321Abstract: A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.Type: GrantFiled: February 19, 2008Date of Patent: August 25, 2009Assignee: Elpida Memory, Inc.Inventors: Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki
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Publication number: 20090201753Abstract: There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.Type: ApplicationFiled: February 6, 2009Publication date: August 13, 2009Inventors: Yoshiro Riho, Jun Suzuki, Yasuhiro Matsumoto, Shuichi Kubouchi, Hiromasa Noda, Yasuji Koshikawa
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Publication number: 20080165611Abstract: A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.Type: ApplicationFiled: February 19, 2008Publication date: July 10, 2008Applicant: ELPIDA MEMORY INC.Inventors: Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki