Abstract: A semiconductor device includes a flip-flop circuit that includes a first and a second latch coupled to the first latch. The first latch stores data in a first operating mode in which power is supplied to the first latch and is shut off in a second operating mode in which power is not supplied to the first latch. The second latch can store the data from the first latch during a transition from the first operating mode to the second operating mode. The first latch can be tested during a first period in the first operating mode. The second latch retains the data from the first latch during the first period and can be tested during a second period beginning in the first operating mode.

Abstract: A semiconductor device includes a flip-flop circuit that includes a first and a second latch coupled to the first latch. The first latch stores data in a first operating mode in which power is supplied to the first latch and is shut off in a second operating mode in which power is not supplied to the first latch. The second latch can store the data from the first latch during a transition from the first operating mode to the second operating mode. The first latch can be tested during a first period in the first operating mode. The second latch retains the data from the first latch during the first period and can be tested during a second period beginning in the first operating mode.

Abstract: According to one embodiment, a semiconductor device includes: a voltage line to which a first voltage is applied; a first circuit configured to operate by using the first voltage; and a second circuit configured to control a connection between the voltage line and the first circuit. The second circuit includes: at least one first switch circuit configured to connect the first circuit and the voltage line based on a first control signal; and a second switch circuit including a plurality of switch sections configured to connect the first circuit and the voltage line based on a plurality of second control signals different from the first control signal.

Abstract: According to one embodiment, a semiconductor device includes: a voltage line to which a first voltage is applied; a first circuit configured to operate by using the first voltage; and a second circuit configured to control a connection between the voltage line and the first circuit. The second circuit includes: at least one first switch circuit configured to connect the first circuit and the voltage line based on a first control signal; and a second switch circuit including a plurality of switch sections configured to connect the first circuit and the voltage line based on a plurality of second control signals different from the first control signal.

Abstract: A semiconductor integrated circuit includes a first register configured to store a first value indicating whether or not a macro is in a state at a first time point, and to update the first value to a second value indicating whether or not the macro is in the state at a second time point after the first time point, and a second register configured to store and retain the first value, and not to update the first value to the second value.

Abstract: An object of the present invention is to solve a problem that, if the state of a macro that is a debug target changes by a factor other than a debugger while the debugger debugs the macro as a target, the debugger becomes unable to continue debugging and the debugging terminates abnormally. In order to solve the aforementioned problem, disclosed is a semiconductor integrated circuit including a first register that stores a value indicating that the macro is in a reset state in response to a reset signal received during debugging of the macro, and a second register that stores a value indicating whether or not the macro has been in the reset state in the past by receiving a reset signal.

Abstract: A resume signal hold circuit holds an assertion of a resume signal instructed while the circuit block is in a stand-by mode. A resume signal mask circuit is provided between the circuit block and the resume signal hold circuit, and masks the signals while the circuit block is in the stand-by mode so that no signal can be input to the circuit block. A power saving control circuit causes the resume signal hold circuit to hold the assertion of the event signal and causes the resume signal mask circuit to mask the signals while the circuit block is in a stand-by mode. The power saving control circuit also causes the resume signal hold circuit to cancel the holding of the assertion of the resume signal after the completion of the resume setting of the circuit block and cancelling of the signal masking by the resume signal mask circuit.

Abstract: A semiconductor integrated circuit includes a scan chain which includes: first flip-flops contained in a first circuit and second flip-flops contained in a second circuit, wherein the first flip-flops and the second flip-flops are connected in a series connection in a scan path test mode to operate as a shift register, and a first selecting circuit configured to selectively output a test data in the scan path test mode and internal state data indicating an internal state of the first flip-flops and read from a memory circuit in a restoring operation in a normal mode to the series connection.

Abstract: When a processor has transitioned to an operation stop state, it is possible to reduce the power consumption of a cache memory while maintaining the consistency of cache data. A multiprocessor system includes first and second processors, a shared memory, first and second cache memories, a consistency management circuit for managing consistency of data stored in the first and second cache memories, a request signal line for transmitting a request signal for a data update request from the consistency management circuit to the first and second cache memories, an information signal line for transmitting an information signal for informing completion of the data update from the first and second cache memories to the consistency management circuit, and a cache power control circuit for controlling supply of a clock signal and power to the first and second cache memories in accordance with the request signal and the information signal.

Abstract: A semiconductor integrated circuit (chip) includes a primary TAP controller and a secondary TAP controller. The primary TAP controller interprets a bit string of n bits included in the group 1 having an m-bit length (m?2) and less than the total number of m bits as an instruction that carries out a processing for a control object and interprets each bit string having an m-bit length as an instruction that carries out no processing for the control object. The m-bit length is obtained by adding a predetermined single bit string to each bit string included in the group 1 consisting of at least two or more bit strings having an n-bit length, respectively. The secondary TAP controller extracts a single bit string denoting an instruction that has an n-bit length and carries out no processing for the control object from each bit string interpreted by the primary TAP controller as an instruction that carries out a processing for the control object, then interprets the single bit string.

Abstract: A resume signal hold circuit holds an assertion of a resume signal instructed while the circuit block is in a stand-by mode. A resume signal mask circuit is provided between the circuit block and the resume signal hold circuit, and masks the signals while the circuit block is in the stand-by mode so that no signal can be input to the circuit block. A power saving control circuit causes the resume signal hold circuit to hold the assertion of the event signal and causes the resume signal mask circuit to mask the signals while the circuit block is in a stand-by mode. The power saving control circuit also causes the resume signal hold circuit to cancel the holding of the assertion of the resume signal after the completion of the resume setting of the circuit block and cancelling of the signal masking by the resume signal mask circuit.

Abstract: A semiconductor integrated circuit includes: a first circuit; and a second circuit configured to control supply of a first power to the first circuit. The first circuit includes: a third circuit comprising a group of flip-flops, whose internal state is erased in response to stop of the supply of the first power; and a fourth circuit in which an internal state of the fourth circuit is saved in retention flip-flops before the supply of the first power is stopped and recovered from the retention flip-flops in response to restart of the supply of the first power.

Abstract: A semiconductor integrated circuit includes a scan chain which includes: first flip-flops contained in a first circuit and second flip-flops contained in a second circuit, wherein the first flip-flops and the second flip-flops are connected in a series connection in a scan path test mode to operate as a shift register, and a first selecting circuit configured to selectively output a test data in the scan path test mode and internal state data indicating an internal state of the first flip-flops and read from a memory circuit in a restoring operation in a normal mode to the series connection.

Abstract: A load/store unit includes a Top register for storing a value retained before loading to a load destination register and a saved register capable of storing data retained to the Top register. When an unaligned instruction evaluation unit determines that a load instruction issued from a instruction decode unit is an unaligned instruction, data stored to the Top register are stored to the saved register in order to make the Top register available to subsequent load instructions issued from the instruction decode unit.

Abstract: An object of the present invention is to solve a problem that, if the state of a macro that is a debug target changes by a factor other than a debugger while the debugger debugs the macro as a target, the debugger becomes unable to continue debugging and the debugging terminates abnormally. In order to solve the aforementioned problem, disclosed is a semiconductor integrated circuit including a first register that stores a value indicating that the macro is in a reset state in response to a reset signal received during debugging of the macro, and a second register that stores a value indicating whether or not the macro has been in the reset state in the past by receiving a reset signal.

Abstract: A semiconductor integrated circuit (chip) includes a primary TAP controller and a secondary TAP controller. The primary TAP controller interprets a bit string of n bits included in the group 1 having an m-bit length (m?2) and less than the total number of m bits as an instruction that carries out a processing for a control object and interprets each bit string having an m-bit length as an instruction that carries out no processing for the control object. The m-bit length is obtained by adding a predetermined single bit string to each bit string included in the group 1 consisting of at least two or more bit strings having an n-bit length, respectively. The secondary TAP controller extracts a single bit string denoting an instruction that has an n-bit length and carries out no processing for the control object from each bit string interpreted by the primary TAP controller as an instruction that carries out a processing for the control object, then interprets the single bit string.

Abstract: A load/store unit includes a Top register for storing a value retained before loading to a load destination register and a saved register capable of storing data retained to the Top register. When an unaligned instruction evaluation unit determines that a load instruction issued from a instruction decode unit is an unaligned instruction, data stored to the Top register are stored to the saved register in order to make the Top register available to subsequent load instructions issued from the instruction decode unit.